void set_hpll_od3_g12a(unsigned int div);
int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd);
+int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd);
int read_hpd_gpio_txlx(void);
int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd);
extern unsigned int hdmitx_get_format_txlx(void);
case MESON_CPU_ID_GXM:
return hdmitx_hpd_hw_op_gxl(cmd);
case MESON_CPU_ID_TXLX:
- case MESON_CPU_ID_G12A:
return hdmitx_hpd_hw_op_txlx(cmd);
+ case MESON_CPU_ID_G12A:
+ return hdmitx_hpd_hw_op_g12a(cmd);
default:
break;
}
default:
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb8282);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x28b0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0);
break;
}
break;
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 2, 16, 2);
break;
default:
- pr_info("Err %s[%d]\n", __func__, __LINE__);
break;
}
}
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 2, 18, 2);
break;
default:
- pr_info("Err %s[%d]\n", __func__, __LINE__);
break;
}
}
break;
}
}
+
+int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case HPD_INIT_DISABLE_PULLUP:
+ hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 25, 1);
+ break;
+ case HPD_INIT_SET_FILTER:
+ hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
+ ((0xa << 12) | (0xa0 << 0)));
+ break;
+ case HPD_IS_HPD_MUXED:
+ ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_6) & (1 << 31));
+ break;
+ case HPD_MUX_HPD:
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 1, 8, 4);
+ hd_set_reg_bits(P_PREG_PAD_GPIO4_O, 1, 8, 1);
+ break;
+ case HPD_UNMUX_HPD:
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 0, 8, 4);
+ hd_set_reg_bits(P_PREG_PAD_GPIO4_O, 0, 8, 1);
+ break;
+ case HPD_READ_HPD_GPIO:
+ ret = hdmitx_rd_reg(HDMITX_DWC_PHY_STAT0) & (1 << 1);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
#define P_PERIPHS_PIN_MUX_11 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define PERIPHS_PIN_MUX_12 0x38 /* register.h:431 */
#define P_PERIPHS_PIN_MUX_12 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_12)
+#define PERIPHS_PIN_MUX_B 0xbb /* register.h:431 */
+#define P_PERIPHS_PIN_MUX_B PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_B)
#define PAD_PULL_UP_REG0 0x3a
#define P_PAD_PULL_UP_REG0 PERIPHS_REG_ADDR(PAD_PULL_UP_REG0)
#define PAD_PULL_UP_EN_REG4 0x4c
#define P_PAD_PULL_UP_EN_REG4 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG4)
+
#define HHI_MEM_PD_REG0 0x40
#define P_HHI_MEM_PD_REG0 HHI_REG_ADDR(HHI_MEM_PD_REG0)
#define HHI_VPU_MEM_PD_REG0 0x41
switch (type) {
case MESON_CPU_ID_G12A:
map = reg_maps_g12a;
- for (i = HDMITX_REG_IDX; i <= HDMITX_SEC_REG_IDX; i++) {
+ for (i = 0; i <= REG_IDX_END; i++) {
map[i].p = ioremap(map[i].phy_addr, map[i].size);
if (!map[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
switch (hdev->chip_type) {
case MESON_CPU_ID_TXLX:
- case MESON_CPU_ID_G12A:
switch (index) {
case CBUS_REG_IDX:
case RESET_CBUS_REG_IDX:
break;
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
+ case MESON_CPU_ID_G12A:
default:
val = readl(TO_PMAP_ADDR(addr));
break;
switch (hdev->chip_type) {
case MESON_CPU_ID_TXLX:
- case MESON_CPU_ID_G12A:
switch (index) {
case CBUS_REG_IDX:
case RESET_CBUS_REG_IDX:
break;
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
+ case MESON_CPU_ID_G12A:
default:
writel(val, TO_PMAP_ADDR(addr));
break;