mailbox: qcom-apcs-ipc: add IPQ5332 APSS clock support

IPQ5332 has the APSS clock controller utilizing the same register space
as the APCS, so provide access to the APSS utilizing a child device like
other IPQ chipsets.

Like IPQ6018, the same controller and driver is used, so utilize IPQ6018
match data for IPQ5332.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index bd61dac..6bbf87c 100644 (file)
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -141,6 +141,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
 
 /* .data is the offset of the ipc register within the global block */
 static const struct of_device_id qcom_apcs_ipc_of_match[] = {
+       { .compatible = "qcom,ipq5332-apcs-apps-global", .data = &ipq6018_apcs_data },
        { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
        { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
        { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },