; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6)