$(shell pkg-config libdrm --cflags-only-I)
C_SOURCES = \
+ r600_asm.c \
r600_buffer.c \
- r600_state2.c \
- evergreen_state.c \
- r600_shader.c \
r600_helper.c \
+ r600_pipe.c \
+ r600_query.c \
r600_resource.c \
+ r600_shader.c \
+ r600_state.c \
r600_texture.c \
- r600_asm.c \
r700_asm.c \
+ evergreen_state.c \
eg_asm.c
include ../../Makefile.template
#include <pipebuffer/pb_buffer.h>
#include "r600.h"
#include "evergreend.h"
-struct radeon_state {
- unsigned dummy;
-};
#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
assert(info->index_bias == 0);
if (rctx->any_user_vbs) {
- r600_upload_user_buffers2(rctx);
+ r600_upload_user_buffers(rctx);
rctx->any_user_vbs = FALSE;
}
draw.index_buffer = rctx->index_buffer.buffer;
draw.index_buffer_offset = draw.start * draw.index_size;
draw.start = 0;
- r600_upload_index_buffer2(rctx, &draw);
+ r600_upload_index_buffer(rctx, &draw);
} else {
draw.index_size = 0;
draw.index_buffer = NULL;
r600_buffer_transfer_unmap, /* transfer_unmap */
u_default_transfer_inline_write /* transfer_inline_write */
};
+
+int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw)
+{
+ struct pipe_resource *upload_buffer = NULL;
+ unsigned index_offset = draw->index_buffer_offset;
+ int ret = 0;
+
+ if (r600_buffer_is_user_buffer(draw->index_buffer)) {
+ ret = u_upload_buffer(rctx->upload_ib,
+ index_offset,
+ draw->count * draw->index_size,
+ draw->index_buffer,
+ &index_offset,
+ &upload_buffer);
+ if (ret) {
+ goto done;
+ }
+ draw->index_buffer_offset = index_offset;
+
+ /* Transfer ownership. */
+ pipe_resource_reference(&draw->index_buffer, upload_buffer);
+ pipe_resource_reference(&upload_buffer, NULL);
+ }
+
+done:
+ return ret;
+}
+
+int r600_upload_user_buffers(struct r600_pipe_context *rctx)
+{
+ enum pipe_error ret = PIPE_OK;
+ int i, nr;
+
+ nr = rctx->vertex_elements->count;
+
+ for (i = 0; i < nr; i++) {
+ struct pipe_vertex_buffer *vb =
+ &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
+
+ if (r600_buffer_is_user_buffer(vb->buffer)) {
+ struct pipe_resource *upload_buffer = NULL;
+ unsigned offset = 0; /*vb->buffer_offset * 4;*/
+ unsigned size = vb->buffer->width0;
+ unsigned upload_offset;
+ ret = u_upload_buffer(rctx->upload_vb,
+ offset, size,
+ vb->buffer,
+ &upload_offset, &upload_buffer);
+ if (ret)
+ return ret;
+
+ pipe_resource_reference(&vb->buffer, NULL);
+ vb->buffer = upload_buffer;
+ vb->buffer_offset = upload_offset;
+ }
+ }
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <util/u_upload_mgr.h>
+#include <util/u_index_modify.h>
+#include <pipebuffer/pb_buffer.h>
+#include "r600.h"
+#include "r600d.h"
+#include "r700_sq.h"
+#include "r600_resource.h"
+#include "r600_shader.h"
+#include "r600_pipe.h"
+#include "r600_state_inlines.h"
+
+/*
+ * pipe_context
+ */
+static void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+ struct pipe_depth_stencil_alpha_state dsa;
+ struct r600_pipe_state *rstate;
+ boolean quirk = false;
+
+ if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+ rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+ quirk = true;
+
+ memset(&dsa, 0, sizeof(dsa));
+
+ if (quirk) {
+ dsa.depth.enabled = 1;
+ dsa.depth.func = PIPE_FUNC_LEQUAL;
+ dsa.stencil[0].enabled = 1;
+ dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+ dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+ dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+ dsa.stencil[0].writemask = 0xff;
+ }
+
+ rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+ r600_pipe_state_add_reg(rstate,
+ R_02880C_DB_SHADER_CONTROL,
+ 0x0,
+ S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028D0C_DB_RENDER_CONTROL,
+ S_028D0C_DEPTH_COPY_ENABLE(1) |
+ S_028D0C_STENCIL_COPY_ENABLE(1) |
+ S_028D0C_COPY_CENTROID(1),
+ S_028D0C_DEPTH_COPY_ENABLE(1) |
+ S_028D0C_STENCIL_COPY_ENABLE(1) |
+ S_028D0C_COPY_CENTROID(1), NULL);
+ return rstate;
+}
+
+static void r600_flush2(struct pipe_context *ctx, unsigned flags,
+ struct pipe_fence_handle **fence)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+#if 0
+ static int dc = 0;
+ char dname[256];
+#endif
+
+ if (!rctx->ctx.pm4_cdwords)
+ return;
+
+ u_upload_flush(rctx->upload_vb);
+ u_upload_flush(rctx->upload_ib);
+
+#if 0
+ sprintf(dname, "gallium-%08d.bof", dc);
+ if (dc < 20) {
+ r600_context_dump_bof(&rctx->ctx, dname);
+ R600_ERR("dumped %s\n", dname);
+ }
+ dc++;
+#endif
+ r600_context_flush(&rctx->ctx);
+}
+
+static void r600_destroy_context(struct pipe_context *context)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
+
+ r600_context_fini(&rctx->ctx);
+ for (int i = 0; i < R600_PIPE_NSTATES; i++) {
+ free(rctx->states[i]);
+ }
+
+ u_upload_destroy(rctx->upload_vb);
+ u_upload_destroy(rctx->upload_ib);
+
+ FREE(rctx);
+}
+
+static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
+{
+ struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
+ struct r600_screen* rscreen = (struct r600_screen *)screen;
+
+ if (rctx == NULL)
+ return NULL;
+ rctx->context.winsys = rscreen->screen.winsys;
+ rctx->context.screen = screen;
+ rctx->context.priv = priv;
+ rctx->context.destroy = r600_destroy_context;
+ rctx->context.flush = r600_flush2;
+
+ /* Easy accessing of screen/winsys. */
+ rctx->screen = rscreen;
+ rctx->radeon = rscreen->radeon;
+ rctx->family = r600_get_family(rctx->radeon);
+
+ r600_init_blit_functions2(rctx);
+ r600_init_query_functions2(rctx);
+ r600_init_context_resource_functions2(rctx);
+
+ switch (r600_get_family(rctx->radeon)) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ rctx->context.draw_vbo = r600_draw_vbo2;
+ r600_init_state_functions2(rctx);
+ if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+ r600_init_config2(rctx);
+ break;
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ rctx->context.draw_vbo = evergreen_draw;
+ evergreen_init_state_functions2(rctx);
+ if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+ evergreen_init_config2(rctx);
+ break;
+ default:
+ R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+
+ rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
+ PIPE_BIND_INDEX_BUFFER);
+ if (rctx->upload_ib == NULL) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+
+ rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
+ PIPE_BIND_VERTEX_BUFFER);
+ if (rctx->upload_vb == NULL) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+
+ rctx->blitter = util_blitter_create(&rctx->context);
+ if (rctx->blitter == NULL) {
+ FREE(rctx);
+ return NULL;
+ }
+
+ LIST_INITHEAD(&rctx->query_list);
+ rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
+
+ r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth2;
+
+ return &rctx->context;
+}
+
+/*
+ * pipe_screen
+ */
+static const char* r600_get_vendor(struct pipe_screen* pscreen)
+{
+ return "X.Org";
+}
+
+static const char* r600_get_name(struct pipe_screen* pscreen)
+{
+ struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+ enum radeon_family family = r600_get_family(rscreen->radeon);
+
+ if (family >= CHIP_R600 && family < CHIP_RV770)
+ return "R600 (HD2XXX,HD3XXX)";
+ else if (family < CHIP_CEDAR)
+ return "R700 (HD4XXX)";
+ else
+ return "EVERGREEN";
+}
+
+static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+ switch (param) {
+ /* Supported features (boolean caps). */
+ case PIPE_CAP_NPOT_TEXTURES:
+ case PIPE_CAP_TWO_SIDED_STENCIL:
+ case PIPE_CAP_GLSL:
+ case PIPE_CAP_DUAL_SOURCE_BLEND:
+ case PIPE_CAP_ANISOTROPIC_FILTER:
+ case PIPE_CAP_POINT_SPRITE:
+ case PIPE_CAP_OCCLUSION_QUERY:
+ case PIPE_CAP_TEXTURE_SHADOW_MAP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
+ case PIPE_CAP_BLEND_EQUATION_SEPARATE:
+ case PIPE_CAP_SM3:
+ case PIPE_CAP_TEXTURE_SWIZZLE:
+ case PIPE_CAP_INDEP_BLEND_ENABLE:
+ case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+ case PIPE_CAP_DEPTH_CLAMP:
+ return 1;
+
+ /* Unsupported features (boolean caps). */
+ case PIPE_CAP_TIMER_QUERY:
+ case PIPE_CAP_STREAM_OUTPUT:
+ case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
+ return 0;
+
+ /* Texturing. */
+ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+ return 14;
+ case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+ /* FIXME allow this once infrastructure is there */
+ return 0;
+ case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+ case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+ return 16;
+
+ /* Render targets. */
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ /* FIXME some r6xx are buggy and can only do 4 */
+ return 8;
+
+ /* Fragment coordinate conventions. */
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+ return 1;
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+ return 0;
+
+ default:
+ R600_ERR("r600: unknown param %d\n", param);
+ return 0;
+ }
+}
+
+static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+ switch (param) {
+ case PIPE_CAP_MAX_LINE_WIDTH:
+ case PIPE_CAP_MAX_LINE_WIDTH_AA:
+ case PIPE_CAP_MAX_POINT_WIDTH:
+ case PIPE_CAP_MAX_POINT_WIDTH_AA:
+ return 8192.0f;
+ case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+ return 16.0f;
+ case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+ return 16.0f;
+ default:
+ R600_ERR("r600: unsupported paramf %d\n", param);
+ return 0.0f;
+ }
+}
+
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+ switch(shader)
+ {
+ case PIPE_SHADER_FRAGMENT:
+ case PIPE_SHADER_VERTEX:
+ break;
+ case PIPE_SHADER_GEOMETRY:
+ /* TODO: support and enable geometry programs */
+ return 0;
+ default:
+ /* TODO: support tessellation on Evergreen */
+ return 0;
+ }
+
+ /* TODO: all these should be fixed, since r600 surely supports much more! */
+ switch (param) {
+ case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+ return 16384;
+ case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+ return 8; /* FIXME */
+ case PIPE_SHADER_CAP_MAX_INPUTS:
+ if(shader == PIPE_SHADER_FRAGMENT)
+ return 10;
+ else
+ return 16;
+ case PIPE_SHADER_CAP_MAX_TEMPS:
+ return 256; //max native temporaries
+ case PIPE_SHADER_CAP_MAX_ADDRS:
+ return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
+ case PIPE_SHADER_CAP_MAX_CONSTS:
+ return 256; //max native parameters
+ case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+ return 1;
+ case PIPE_SHADER_CAP_MAX_PREDS:
+ return 0; /* FIXME */
+ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static boolean r600_is_format_supported(struct pipe_screen* screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned sample_count,
+ unsigned usage,
+ unsigned geom_flags)
+{
+ unsigned retval = 0;
+ if (target >= PIPE_MAX_TEXTURE_TYPES) {
+ R600_ERR("r600: unsupported texture type %d\n", target);
+ return FALSE;
+ }
+
+ /* Multisample */
+ if (sample_count > 1)
+ return FALSE;
+
+ if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+ r600_is_sampler_format_supported(format)) {
+ retval |= PIPE_BIND_SAMPLER_VIEW;
+ }
+
+ if ((usage & (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED)) &&
+ r600_is_colorbuffer_format_supported(format)) {
+ retval |= usage &
+ (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED);
+ }
+
+ if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+ r600_is_zs_format_supported(format)) {
+ retval |= PIPE_BIND_DEPTH_STENCIL;
+ }
+
+ if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+ r600_is_vertex_format_supported(format))
+ retval |= PIPE_BIND_VERTEX_BUFFER;
+
+ if (usage & PIPE_BIND_TRANSFER_READ)
+ retval |= PIPE_BIND_TRANSFER_READ;
+ if (usage & PIPE_BIND_TRANSFER_WRITE)
+ retval |= PIPE_BIND_TRANSFER_WRITE;
+
+ return retval == usage;
+}
+
+static void r600_destroy_screen(struct pipe_screen* pscreen)
+{
+ struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+
+ if (rscreen == NULL)
+ return;
+ FREE(rscreen);
+}
+
+
+struct pipe_screen *r600_screen_create2(struct radeon *radeon)
+{
+ struct r600_screen *rscreen;
+
+ rscreen = CALLOC_STRUCT(r600_screen);
+ if (rscreen == NULL) {
+ return NULL;
+ }
+
+ rscreen->radeon = radeon;
+ rscreen->screen.winsys = (struct pipe_winsys*)radeon;
+ rscreen->screen.destroy = r600_destroy_screen;
+ rscreen->screen.get_name = r600_get_name;
+ rscreen->screen.get_vendor = r600_get_vendor;
+ rscreen->screen.get_param = r600_get_param;
+ rscreen->screen.get_shader_param = r600_get_shader_param;
+ rscreen->screen.get_paramf = r600_get_paramf;
+ rscreen->screen.is_format_supported = r600_is_format_supported;
+ rscreen->screen.context_create = r600_create_context2;
+ r600_init_screen_texture_functions(&rscreen->screen);
+ r600_init_screen_resource_functions(&rscreen->screen);
+
+ return &rscreen->screen;
+}
/* r600_state2.c */
int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader);
int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens);
-int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw);
-int r600_upload_user_buffers2(struct r600_pipe_context *rctx);
void r600_translate_index_buffer2(struct r600_pipe_context *r600,
struct pipe_resource **index_buffer,
unsigned *index_size,
}
#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+/* r600_blit.c */
+void r600_init_blit_functions2(struct r600_pipe_context *rctx);
+int r600_blit_uncompress_depth2(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
/* r600_buffer.c */
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
unsigned face, unsigned level);
struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
struct winsys_handle *whandle);
+int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw);
+int r600_upload_user_buffers(struct r600_pipe_context *rctx);
+
+/* r600_query.c */
+void r600_init_query_functions2(struct r600_pipe_context *rctx);
+
+/* r600_resource.c */
+void r600_init_context_resource_functions2(struct r600_pipe_context *r600);
+
+/* r600_state.c */
+void r600_init_state_functions2(struct r600_pipe_context *rctx);
+void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void r600_init_config2(struct r600_pipe_context *rctx);
+
+/* r600_helper.h */
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+
+/* r600_texture.c */
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
#endif
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* TODO:
+ * - fix mask for depth control & cull for query
+ */
+#include "r600_pipe.h"
+
+static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
+}
+
+static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
+}
+
+static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_query *rquery = (struct r600_query *)query;
+
+ rquery->result = 0;
+ rquery->num_results = 0;
+ r600_query_begin(&rctx->ctx, (struct r600_query *)query);
+}
+
+static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ r600_query_end(&rctx->ctx, (struct r600_query *)query);
+}
+
+static boolean r600_get_query_result(struct pipe_context *ctx,
+ struct pipe_query *query,
+ boolean wait, void *vresult)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_query *rquery = (struct r600_query *)query;
+
+ if (rquery->num_results) {
+ ctx->flush(ctx, 0, NULL);
+ }
+ return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
+}
+
+void r600_init_query_functions2(struct r600_pipe_context *rctx)
+{
+ rctx->context.create_query = r600_create_query;
+ rctx->context.destroy_query = r600_destroy_query;
+ rctx->context.begin_query = r600_begin_query;
+ rctx->context.end_query = r600_end_query;
+ rctx->context.get_query_result = r600_get_query_result;
+}
screen->resource_destroy = u_resource_destroy_vtbl;
screen->user_buffer_create = r600_user_buffer_create;
}
+
+void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
+{
+ r600->context.get_transfer = u_get_transfer_vtbl;
+ r600->context.transfer_map = u_transfer_map_vtbl;
+ r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+ r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+ r600->context.transfer_destroy = u_transfer_destroy_vtbl;
+ r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
+ r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
+}
+
#include <stdio.h>
#include <errno.h>
+static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned spi_vs_out_id[10];
+ unsigned i, tmp;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ /* so far never got proper semantic id from tgsi */
+ for (i = 0; i < 10; i++) {
+ spi_vs_out_id[i] = 0;
+ }
+ for (i = 0; i < 32; i++) {
+ tmp = i << ((i & 3) * 8);
+ spi_vs_out_id[i / 4] |= tmp;
+ }
+ for (i = 0; i < 10; i++) {
+ r600_pipe_state_add_reg(rstate,
+ R_028614_SPI_VS_OUT_ID_0 + i * 4,
+ spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+ }
+
+ r600_pipe_state_add_reg(rstate,
+ R_0286C4_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028868_SQ_PGM_RESOURCES_VS,
+ S_028868_NUM_GPRS(rshader->bc.ngpr) |
+ S_028868_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_0288A4_SQ_PGM_RESOURCES_FS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_0288D0_SQ_PGM_CF_OFFSET_VS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_0288DC_SQ_PGM_CF_OFFSET_FS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028858_SQ_PGM_START_VS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate,
+ R_028894_SQ_PGM_START_FS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+}
+
+int r600_find_vs_semantic_index2(struct r600_shader *vs,
+ struct r600_shader *ps, int id)
+{
+ struct r600_shader_io *input = &ps->input[id];
+
+ for (int i = 0; i < vs->noutput; i++) {
+ if (input->name == vs->output[i].name &&
+ input->sid == vs->output[i].sid) {
+ return i - 1;
+ }
+ }
+ return 0;
+}
+
+static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
+ boolean have_pos = FALSE, have_face = FALSE;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ for (i = 0; i < rshader->ninput; i++) {
+ tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx->vs_shader->shader, rshader, i));
+ tmp |= S_028644_SEL_CENTROID(1);
+ if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+ have_pos = TRUE;
+ if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+ tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+ }
+ if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
+ have_face = TRUE;
+ if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+ r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+ }
+ for (i = 0; i < rshader->noutput; i++) {
+ r600_pipe_state_add_reg(rstate,
+ R_02880C_DB_SHADER_CONTROL,
+ S_02880C_Z_EXPORT_ENABLE(1),
+ S_02880C_Z_EXPORT_ENABLE(1), NULL);
+ }
+
+ exports_ps = 0;
+ num_cout = 0;
+ for (i = 0; i < rshader->noutput; i++) {
+ if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+ exports_ps |= 1;
+ else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+ num_cout++;
+ }
+ }
+ exports_ps |= S_028854_EXPORT_COLORS(num_cout);
+ if (!exports_ps) {
+ /* always at least export 1 component per pixel */
+ exports_ps = 2;
+ }
+
+ spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
+ S_0286CC_PERSP_GRADIENT_ENA(1);
+ spi_input_z = 0;
+ if (have_pos) {
+ spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
+ S_0286CC_BARYC_SAMPLE_CNTL(1);
+ spi_input_z |= 1;
+ }
+ r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028840_SQ_PGM_START_PS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate,
+ R_028850_SQ_PGM_RESOURCES_PS,
+ S_028868_NUM_GPRS(rshader->bc.ngpr) |
+ S_028868_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028854_SQ_PGM_EXPORTS_PS,
+ exports_ps, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_0288CC_SQ_PGM_CF_OFFSET_PS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+
+ if (rshader->uses_kill) {
+ /* only set some bits here, the other bits are set in the dsa state */
+ r600_pipe_state_add_reg(rstate,
+ R_02880C_DB_SHADER_CONTROL,
+ S_02880C_KILL_ENABLE(1),
+ S_02880C_KILL_ENABLE(1), NULL);
+ }
+}
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_shader *rshader = &shader->shader;
+ void *ptr;
+
+ /* copy new shader */
+ if (shader->bo == NULL) {
+ shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
+ if (shader->bo == NULL) {
+ return -ENOMEM;
+ }
+ ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
+ memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
+ radeon_ws_bo_unmap(rctx->radeon, shader->bo);
+ }
+ /* build state */
+ rshader->flat_shade = rctx->flatshade;
+ switch (rshader->processor_type) {
+ case TGSI_PROCESSOR_VERTEX:
+ if (rshader->family >= CHIP_CEDAR) {
+ evergreen_pipe_shader_vs(ctx, shader);
+ } else {
+ r600_pipe_shader_vs(ctx, shader);
+ }
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ if (rshader->family >= CHIP_CEDAR) {
+ evergreen_pipe_shader_ps(ctx, shader);
+ } else {
+ r600_pipe_shader_ps(ctx, shader);
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+ r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+ return 0;
+}
+
+static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_shader *shader = &rshader->shader;
+ const struct util_format_description *desc;
+ enum pipe_format resource_format[160];
+ unsigned i, nresources = 0;
+ struct r600_bc *bc = &shader->bc;
+ struct r600_bc_cf *cf;
+ struct r600_bc_vtx *vtx;
+
+ if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
+ return 0;
+ if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
+ return 0;
+ }
+ rshader->vertex_elements = *rctx->vertex_elements;
+ for (i = 0; i < rctx->vertex_elements->count; i++) {
+ resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
+ }
+ radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
+ LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
+ switch (cf->inst) {
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ desc = util_format_description(resource_format[vtx->buffer_id]);
+ if (desc == NULL) {
+ R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
+ return -EINVAL;
+ }
+ vtx->dst_sel_x = desc->swizzle[0];
+ vtx->dst_sel_y = desc->swizzle[1];
+ vtx->dst_sel_z = desc->swizzle[2];
+ vtx->dst_sel_w = desc->swizzle[3];
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return r600_bc_build(&shader->bc);
+}
+
+int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ int r;
+
+ if (shader == NULL)
+ return -EINVAL;
+ /* there should be enough input */
+ if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
+ R600_ERR("%d resources provided, expecting %d\n",
+ rctx->vertex_elements->count, shader->shader.bc.nresource);
+ return -EINVAL;
+ }
+ r = r600_shader_update(ctx, shader);
+ if (r)
+ return r;
+ return r600_pipe_shader(ctx, shader);
+}
+
+int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
+int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ int r;
+
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
+ shader->shader.family = r600_get_family(rctx->radeon);
+ r = r600_shader_from_tgsi(tokens, &shader->shader);
+ if (r) {
+ R600_ERR("translation from TGSI failed !\n");
+ return r;
+ }
+ r = r600_bc_build(&shader->shader.bc);
+ if (r) {
+ R600_ERR("building bytecode failed !\n");
+ return r;
+ }
+//fprintf(stderr, "______________________________________________________________\n");
+ return 0;
+}
+
+/*
+ * tgsi -> r600 shader
+ */
struct r600_shader_tgsi_instruction;
struct r600_shader_ctx {
#include "r600.h"
#include "r600d.h"
#include "r700_sq.h"
-struct radeon_state {
- unsigned dummy;
-};
#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
#include "r600_state_inlines.h"
-/* r600_shader.c */
-static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
- struct r600_pipe_state *rstate = &shader->rstate;
- struct r600_shader *rshader = &shader->shader;
- unsigned spi_vs_out_id[10];
- unsigned i, tmp;
-
- /* clear previous register */
- rstate->nregs = 0;
-
- /* so far never got proper semantic id from tgsi */
- for (i = 0; i < 10; i++) {
- spi_vs_out_id[i] = 0;
- }
- for (i = 0; i < 32; i++) {
- tmp = i << ((i & 3) * 8);
- spi_vs_out_id[i / 4] |= tmp;
- }
- for (i = 0; i < 10; i++) {
- r600_pipe_state_add_reg(rstate,
- R_028614_SPI_VS_OUT_ID_0 + i * 4,
- spi_vs_out_id[i], 0xFFFFFFFF, NULL);
- }
-
- r600_pipe_state_add_reg(rstate,
- R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
- 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_028868_SQ_PGM_RESOURCES_VS,
- S_028868_NUM_GPRS(rshader->bc.ngpr) |
- S_028868_STACK_SIZE(rshader->bc.nstack),
- 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_0288A4_SQ_PGM_RESOURCES_FS,
- 0x00000000, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_0288D0_SQ_PGM_CF_OFFSET_VS,
- 0x00000000, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_0288DC_SQ_PGM_CF_OFFSET_FS,
- 0x00000000, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_028858_SQ_PGM_START_VS,
- 0x00000000, 0xFFFFFFFF, shader->bo);
- r600_pipe_state_add_reg(rstate,
- R_028894_SQ_PGM_START_FS,
- 0x00000000, 0xFFFFFFFF, shader->bo);
-}
-
-int r600_find_vs_semantic_index2(struct r600_shader *vs,
- struct r600_shader *ps, int id)
-{
- struct r600_shader_io *input = &ps->input[id];
-
- for (int i = 0; i < vs->noutput; i++) {
- if (input->name == vs->output[i].name &&
- input->sid == vs->output[i].sid) {
- return i - 1;
- }
- }
- return 0;
-}
-
-static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_pipe_state *rstate = &shader->rstate;
- struct r600_shader *rshader = &shader->shader;
- unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
- boolean have_pos = FALSE, have_face = FALSE;
-
- /* clear previous register */
- rstate->nregs = 0;
-
- for (i = 0; i < rshader->ninput; i++) {
- tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx->vs_shader->shader, rshader, i));
- tmp |= S_028644_SEL_CENTROID(1);
- if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
- have_pos = TRUE;
- if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
- rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
- rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
- tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
- }
- if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
- have_face = TRUE;
- if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
- rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
- tmp |= S_028644_PT_SPRITE_TEX(1);
- }
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
- }
- for (i = 0; i < rshader->noutput; i++) {
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
- S_02880C_Z_EXPORT_ENABLE(1),
- S_02880C_Z_EXPORT_ENABLE(1), NULL);
- }
-
- exports_ps = 0;
- num_cout = 0;
- for (i = 0; i < rshader->noutput; i++) {
- if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
- exports_ps |= 1;
- else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
- num_cout++;
- }
- }
- exports_ps |= S_028854_EXPORT_COLORS(num_cout);
- if (!exports_ps) {
- /* always at least export 1 component per pixel */
- exports_ps = 2;
- }
-
- spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
- S_0286CC_PERSP_GRADIENT_ENA(1);
- spi_input_z = 0;
- if (have_pos) {
- spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
- S_0286CC_BARYC_SAMPLE_CNTL(1);
- spi_input_z |= 1;
- }
- r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_028840_SQ_PGM_START_PS,
- 0x00000000, 0xFFFFFFFF, shader->bo);
- r600_pipe_state_add_reg(rstate,
- R_028850_SQ_PGM_RESOURCES_PS,
- S_028868_NUM_GPRS(rshader->bc.ngpr) |
- S_028868_STACK_SIZE(rshader->bc.nstack),
- 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_028854_SQ_PGM_EXPORTS_PS,
- exports_ps, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate,
- R_0288CC_SQ_PGM_CF_OFFSET_PS,
- 0x00000000, 0xFFFFFFFF, NULL);
-
- if (rshader->uses_kill) {
- /* only set some bits here, the other bits are set in the dsa state */
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
- S_02880C_KILL_ENABLE(1),
- S_02880C_KILL_ENABLE(1), NULL);
- }
-}
-
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_shader *rshader = &shader->shader;
- void *ptr;
-
- /* copy new shader */
- if (shader->bo == NULL) {
- shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
- if (shader->bo == NULL) {
- return -ENOMEM;
- }
- ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
- memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
- radeon_ws_bo_unmap(rctx->radeon, shader->bo);
- }
- /* build state */
- rshader->flat_shade = rctx->flatshade;
- switch (rshader->processor_type) {
- case TGSI_PROCESSOR_VERTEX:
- if (rshader->family >= CHIP_CEDAR) {
- evergreen_pipe_shader_vs(ctx, shader);
- } else {
- r600_pipe_shader_vs(ctx, shader);
- }
- break;
- case TGSI_PROCESSOR_FRAGMENT:
- if (rshader->family >= CHIP_CEDAR) {
- evergreen_pipe_shader_ps(ctx, shader);
- } else {
- r600_pipe_shader_ps(ctx, shader);
- }
- break;
- default:
- return -EINVAL;
- }
- r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
- return 0;
-}
-
-static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_shader *shader = &rshader->shader;
- const struct util_format_description *desc;
- enum pipe_format resource_format[160];
- unsigned i, nresources = 0;
- struct r600_bc *bc = &shader->bc;
- struct r600_bc_cf *cf;
- struct r600_bc_vtx *vtx;
-
- if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
- return 0;
- if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
- return 0;
- }
- rshader->vertex_elements = *rctx->vertex_elements;
- for (i = 0; i < rctx->vertex_elements->count; i++) {
- resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
- }
- radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
- LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
- switch (cf->inst) {
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
- LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
- desc = util_format_description(resource_format[vtx->buffer_id]);
- if (desc == NULL) {
- R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
- return -EINVAL;
- }
- vtx->dst_sel_x = desc->swizzle[0];
- vtx->dst_sel_y = desc->swizzle[1];
- vtx->dst_sel_z = desc->swizzle[2];
- vtx->dst_sel_w = desc->swizzle[3];
- }
- break;
- default:
- break;
- }
- }
- return r600_bc_build(&shader->bc);
-}
-
-int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- int r;
-
- if (shader == NULL)
- return -EINVAL;
- /* there should be enough input */
- if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
- R600_ERR("%d resources provided, expecting %d\n",
- rctx->vertex_elements->count, shader->shader.bc.nresource);
- return -EINVAL;
- }
- r = r600_shader_update(ctx, shader);
- if (r)
- return r;
- return r600_pipe_shader(ctx, shader);
-}
-
-int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
-int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- int r;
-
-//fprintf(stderr, "--------------------------------------------------------------\n");
-//tgsi_dump(tokens, 0);
- shader->shader.family = r600_get_family(rctx->radeon);
- r = r600_shader_from_tgsi(tokens, &shader->shader);
- if (r) {
- R600_ERR("translation from TGSI failed !\n");
- return r;
- }
- r = r600_bc_build(&shader->shader.bc);
- if (r) {
- R600_ERR("building bytecode failed !\n");
- return r;
- }
-//fprintf(stderr, "______________________________________________________________\n");
- return 0;
-}
-/* r600_shader.c END */
-
-static const char* r600_get_vendor(struct pipe_screen* pscreen)
-{
- return "X.Org";
-}
-
-static const char* r600_get_name(struct pipe_screen* pscreen)
-{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- enum radeon_family family = r600_get_family(rscreen->radeon);
-
- if (family >= CHIP_R600 && family < CHIP_RV770)
- return "R600 (HD2XXX,HD3XXX)";
- else if (family < CHIP_CEDAR)
- return "R700 (HD4XXX)";
- else
- return "EVERGREEN";
-}
-
-static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
-{
- switch (param) {
- /* Supported features (boolean caps). */
- case PIPE_CAP_NPOT_TEXTURES:
- case PIPE_CAP_TWO_SIDED_STENCIL:
- case PIPE_CAP_GLSL:
- case PIPE_CAP_DUAL_SOURCE_BLEND:
- case PIPE_CAP_ANISOTROPIC_FILTER:
- case PIPE_CAP_POINT_SPRITE:
- case PIPE_CAP_OCCLUSION_QUERY:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
- case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
- case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
- case PIPE_CAP_BLEND_EQUATION_SEPARATE:
- case PIPE_CAP_SM3:
- case PIPE_CAP_TEXTURE_SWIZZLE:
- case PIPE_CAP_INDEP_BLEND_ENABLE:
- case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
- case PIPE_CAP_DEPTH_CLAMP:
- return 1;
-
- /* Unsupported features (boolean caps). */
- case PIPE_CAP_TIMER_QUERY:
- case PIPE_CAP_STREAM_OUTPUT:
- case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
- return 0;
-
- /* Texturing. */
- case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
- case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 14;
- case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
- /* FIXME allow this once infrastructure is there */
- return 0;
- case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
- case PIPE_CAP_MAX_COMBINED_SAMPLERS:
- return 16;
-
- /* Render targets. */
- case PIPE_CAP_MAX_RENDER_TARGETS:
- /* FIXME some r6xx are buggy and can only do 4 */
- return 8;
-
- /* Fragment coordinate conventions. */
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
- return 1;
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- return 0;
-
- default:
- R600_ERR("r600: unknown param %d\n", param);
- return 0;
- }
-}
-
-static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
-{
- switch (param) {
- case PIPE_CAP_MAX_LINE_WIDTH:
- case PIPE_CAP_MAX_LINE_WIDTH_AA:
- case PIPE_CAP_MAX_POINT_WIDTH:
- case PIPE_CAP_MAX_POINT_WIDTH_AA:
- return 8192.0f;
- case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
- return 16.0f;
- case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
- return 16.0f;
- default:
- R600_ERR("r600: unsupported paramf %d\n", param);
- return 0.0f;
- }
-}
-
-static boolean r600_is_format_supported(struct pipe_screen* screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned usage,
- unsigned geom_flags)
-{
- unsigned retval = 0;
- if (target >= PIPE_MAX_TEXTURE_TYPES) {
- R600_ERR("r600: unsupported texture type %d\n", target);
- return FALSE;
- }
-
- /* Multisample */
- if (sample_count > 1)
- return FALSE;
-
- if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
- r600_is_sampler_format_supported(format)) {
- retval |= PIPE_BIND_SAMPLER_VIEW;
- }
-
- if ((usage & (PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED)) &&
- r600_is_colorbuffer_format_supported(format)) {
- retval |= usage &
- (PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED);
- }
-
- if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
- r600_is_zs_format_supported(format)) {
- retval |= PIPE_BIND_DEPTH_STENCIL;
- }
-
- if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
- r600_is_vertex_format_supported(format))
- retval |= PIPE_BIND_VERTEX_BUFFER;
-
- if (usage & PIPE_BIND_TRANSFER_READ)
- retval |= PIPE_BIND_TRANSFER_READ;
- if (usage & PIPE_BIND_TRANSFER_WRITE)
- retval |= PIPE_BIND_TRANSFER_WRITE;
-
- return retval == usage;
-}
-
-static void r600_destroy_screen(struct pipe_screen* pscreen)
-{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
-
- if (rscreen == NULL)
- return;
- FREE(rscreen);
-}
-
-int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
static void r600_draw_common(struct r600_drawl *draw)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
}
}
-static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
+void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_drawl draw;
if (rctx->any_user_vbs) {
- r600_upload_user_buffers2(rctx);
+ r600_upload_user_buffers(rctx);
rctx->any_user_vbs = FALSE;
}
pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
draw.index_buffer_offset = draw.start * draw.index_size;
draw.start = 0;
- r600_upload_index_buffer2(rctx, &draw);
+ r600_upload_index_buffer(rctx, &draw);
} else {
draw.index_size = 0;
draw.index_buffer = NULL;
pipe_resource_reference(&draw.index_buffer, NULL);
}
-static void r600_flush2(struct pipe_context *ctx, unsigned flags,
- struct pipe_fence_handle **fence)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-#if 0
- static int dc = 0;
- char dname[256];
-#endif
-
- if (!rctx->ctx.pm4_cdwords)
- return;
-
- u_upload_flush(rctx->upload_vb);
- u_upload_flush(rctx->upload_ib);
-
-#if 0
- sprintf(dname, "gallium-%08d.bof", dc);
- if (dc < 20) {
- r600_context_dump_bof(&rctx->ctx, dname);
- R600_ERR("dumped %s\n", dname);
- }
- dc++;
-#endif
- r600_context_flush(&rctx->ctx);
-}
-
-static void r600_destroy_context(struct pipe_context *context)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
-
- r600_context_fini(&rctx->ctx);
- for (int i = 0; i < R600_PIPE_NSTATES; i++) {
- free(rctx->states[i]);
- }
-
- u_upload_destroy(rctx->upload_vb);
- u_upload_destroy(rctx->upload_ib);
-
- FREE(rctx);
-}
static void r600_blitter_save_states(struct pipe_context *ctx)
{
src, subsrc, srcx, srcy, srcz, width, height);
}
-static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
+void r600_init_blit_functions2(struct r600_pipe_context *rctx)
{
rctx->context.clear = r600_clear;
rctx->context.clear_render_target = r600_clear_render_target;
rctx->context.resource_copy_region = r600_resource_copy_region;
}
-static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
-{
- r600->context.get_transfer = u_get_transfer_vtbl;
- r600->context.transfer_map = u_transfer_map_vtbl;
- r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
- r600->context.transfer_unmap = u_transfer_unmap_vtbl;
- r600->context.transfer_destroy = u_transfer_destroy_vtbl;
- r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
- r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
-}
-
static void r600_set_blend_color(struct pipe_context *ctx,
const struct pipe_blend_color *state)
{
free(shader);
}
-static void r600_init_state_functions2(struct r600_pipe_context *rctx)
+void r600_init_state_functions2(struct r600_pipe_context *rctx)
{
rctx->context.create_blend_state = r600_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
}
-static void r600_init_config2(struct r600_pipe_context *rctx)
+void r600_init_config2(struct r600_pipe_context *rctx)
{
int ps_prio;
int vs_prio;
r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
-
-static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
- return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
-}
-
-static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
- r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
-}
-
-static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_query *rquery = (struct r600_query *)query;
-
- rquery->result = 0;
- rquery->num_results = 0;
- r600_query_begin(&rctx->ctx, (struct r600_query *)query);
-}
-
-static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
- r600_query_end(&rctx->ctx, (struct r600_query *)query);
-}
-
-static boolean r600_get_query_result(struct pipe_context *ctx,
- struct pipe_query *query,
- boolean wait, void *vresult)
-{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_query *rquery = (struct r600_query *)query;
-
- if (rquery->num_results) {
- ctx->flush(ctx, 0, NULL);
- }
- return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
-}
-
-static void r600_init_query_functions2(struct r600_pipe_context *rctx)
-{
- rctx->context.create_query = r600_create_query;
- rctx->context.destroy_query = r600_destroy_query;
- rctx->context.begin_query = r600_begin_query;
- rctx->context.end_query = r600_end_query;
- rctx->context.get_query_result = r600_get_query_result;
-}
-
-static void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
-{
- struct pipe_depth_stencil_alpha_state dsa;
- struct r600_pipe_state *rstate;
- boolean quirk = false;
-
- if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
- rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
- quirk = true;
-
- memset(&dsa, 0, sizeof(dsa));
-
- if (quirk) {
- dsa.depth.enabled = 1;
- dsa.depth.func = PIPE_FUNC_LEQUAL;
- dsa.stencil[0].enabled = 1;
- dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
- dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
- dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
- dsa.stencil[0].writemask = 0xff;
- }
-
- rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
- r600_pipe_state_add_reg(rstate,
- R_02880C_DB_SHADER_CONTROL,
- 0x0,
- S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
- r600_pipe_state_add_reg(rstate,
- R_028D0C_DB_RENDER_CONTROL,
- S_028D0C_DEPTH_COPY_ENABLE(1) |
- S_028D0C_STENCIL_COPY_ENABLE(1) |
- S_028D0C_COPY_CENTROID(1),
- S_028D0C_DEPTH_COPY_ENABLE(1) |
- S_028D0C_STENCIL_COPY_ENABLE(1) |
- S_028D0C_COPY_CENTROID(1), NULL);
- return rstate;
-}
-
-static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
-{
- struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
- struct r600_screen* rscreen = (struct r600_screen *)screen;
-
- if (rctx == NULL)
- return NULL;
- rctx->context.winsys = rscreen->screen.winsys;
- rctx->context.screen = screen;
- rctx->context.priv = priv;
- rctx->context.destroy = r600_destroy_context;
- rctx->context.flush = r600_flush2;
-
- /* Easy accessing of screen/winsys. */
- rctx->screen = rscreen;
- rctx->radeon = rscreen->radeon;
- rctx->family = r600_get_family(rctx->radeon);
-
- r600_init_blit_functions2(rctx);
- r600_init_query_functions2(rctx);
- r600_init_context_resource_functions2(rctx);
-
- switch (r600_get_family(rctx->radeon)) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- case CHIP_RV770:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_RV740:
- rctx->context.draw_vbo = r600_draw_vbo2;
- r600_init_state_functions2(rctx);
- if (r600_context_init(&rctx->ctx, rctx->radeon)) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
- r600_init_config2(rctx);
- break;
- case CHIP_CEDAR:
- case CHIP_REDWOOD:
- case CHIP_JUNIPER:
- case CHIP_CYPRESS:
- case CHIP_HEMLOCK:
- rctx->context.draw_vbo = evergreen_draw;
- evergreen_init_state_functions2(rctx);
- if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
- evergreen_init_config2(rctx);
- break;
- default:
- R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
- r600_destroy_context(&rctx->context);
- return NULL;
- }
-
- rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
- PIPE_BIND_INDEX_BUFFER);
- if (rctx->upload_ib == NULL) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
-
- rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
- PIPE_BIND_VERTEX_BUFFER);
- if (rctx->upload_vb == NULL) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
-
- rctx->blitter = util_blitter_create(&rctx->context);
- if (rctx->blitter == NULL) {
- FREE(rctx);
- return NULL;
- }
-
- LIST_INITHEAD(&rctx->query_list);
- rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
-
- r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth2;
-
- return &rctx->context;
-}
-
-static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
-{
- switch(shader)
- {
- case PIPE_SHADER_FRAGMENT:
- case PIPE_SHADER_VERTEX:
- break;
- case PIPE_SHADER_GEOMETRY:
- /* TODO: support and enable geometry programs */
- return 0;
- default:
- /* TODO: support tessellation on Evergreen */
- return 0;
- }
-
- /* TODO: all these should be fixed, since r600 surely supports much more! */
- switch (param) {
- case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
- case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
- case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
- case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
- return 16384;
- case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
- return 8; /* FIXME */
- case PIPE_SHADER_CAP_MAX_INPUTS:
- if(shader == PIPE_SHADER_FRAGMENT)
- return 10;
- else
- return 16;
- case PIPE_SHADER_CAP_MAX_TEMPS:
- return 256; //max native temporaries
- case PIPE_SHADER_CAP_MAX_ADDRS:
- return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
- case PIPE_SHADER_CAP_MAX_CONSTS:
- return 256; //max native parameters
- case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* FIXME */
- case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
- return 1;
- default:
- return 0;
- }
-}
-
-struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
- const struct pipe_resource *templ);
-struct pipe_resource *r600_user_buffer_create2(struct pipe_screen *screen,
- void *ptr, unsigned bytes,
- unsigned bind)
-{
- struct pipe_resource *resource;
- struct r600_resource *rresource;
- struct pipe_resource desc;
- struct radeon *radeon = (struct radeon *)screen->winsys;
- void *rptr;
-
- desc.screen = screen;
- desc.target = PIPE_BUFFER;
- desc.format = PIPE_FORMAT_R8_UNORM;
- desc.usage = PIPE_USAGE_IMMUTABLE;
- desc.bind = bind;
- desc.width0 = bytes;
- desc.height0 = 1;
- desc.depth0 = 1;
- desc.flags = 0;
- resource = r600_buffer_create(screen, &desc);
- if (resource == NULL) {
- return NULL;
- }
-
- rresource = (struct r600_resource *)resource;
- rptr = radeon_ws_bo_map(radeon, rresource->bo, 0, NULL);
- memcpy(rptr, ptr, bytes);
- radeon_ws_bo_unmap(radeon, rresource->bo);
-
- return resource;
-}
-
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-struct pipe_screen *r600_screen_create2(struct radeon *radeon)
-{
- struct r600_screen *rscreen;
-
- rscreen = CALLOC_STRUCT(r600_screen);
- if (rscreen == NULL) {
- return NULL;
- }
-
- rscreen->radeon = radeon;
- rscreen->screen.winsys = (struct pipe_winsys*)radeon;
- rscreen->screen.destroy = r600_destroy_screen;
- rscreen->screen.get_name = r600_get_name;
- rscreen->screen.get_vendor = r600_get_vendor;
- rscreen->screen.get_param = r600_get_param;
- rscreen->screen.get_shader_param = r600_get_shader_param;
- rscreen->screen.get_paramf = r600_get_paramf;
- rscreen->screen.is_format_supported = r600_is_format_supported;
- rscreen->screen.context_create = r600_create_context2;
- r600_init_screen_texture_functions(&rscreen->screen);
- r600_init_screen_resource_functions(&rscreen->screen);
-// rscreen->screen.user_buffer_create = r600_user_buffer_create2;
-
- return &rscreen->screen;
-}
-
-int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw)
-{
- struct pipe_resource *upload_buffer = NULL;
- unsigned index_offset = draw->index_buffer_offset;
- int ret = 0;
-
- if (r600_buffer_is_user_buffer(draw->index_buffer)) {
- ret = u_upload_buffer(rctx->upload_ib,
- index_offset,
- draw->count * draw->index_size,
- draw->index_buffer,
- &index_offset,
- &upload_buffer);
- if (ret) {
- goto done;
- }
- draw->index_buffer_offset = index_offset;
-
- /* Transfer ownership. */
- pipe_resource_reference(&draw->index_buffer, upload_buffer);
- pipe_resource_reference(&upload_buffer, NULL);
- }
-
-done:
- return ret;
-}
-
-int r600_upload_user_buffers2(struct r600_pipe_context *rctx)
-{
- enum pipe_error ret = PIPE_OK;
- int i, nr;
-
- nr = rctx->vertex_elements->count;
-
- for (i = 0; i < nr; i++) {
- struct pipe_vertex_buffer *vb =
- &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
-
- if (r600_buffer_is_user_buffer(vb->buffer)) {
- struct pipe_resource *upload_buffer = NULL;
- unsigned offset = 0; /*vb->buffer_offset * 4;*/
- unsigned size = vb->buffer->width0;
- unsigned upload_offset;
- ret = u_upload_buffer(rctx->upload_vb,
- offset, size,
- vb->buffer,
- &upload_offset, &upload_buffer);
- if (ret)
- return ret;
-
- pipe_resource_reference(&vb->buffer, NULL);
- vb->buffer = upload_buffer;
- vb->buffer_offset = upload_offset;
- }
- }
- return ret;
-}
+++ /dev/null
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef RADEON_H
-#define RADEON_H
-
-#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
-
-#include <stdint.h>
-
-#include <pipe/p_compiler.h>
-
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-struct radeon;
-
-enum radeon_family {
- CHIP_UNKNOWN,
- CHIP_R100,
- CHIP_RV100,
- CHIP_RS100,
- CHIP_RV200,
- CHIP_RS200,
- CHIP_R200,
- CHIP_RV250,
- CHIP_RS300,
- CHIP_RV280,
- CHIP_R300,
- CHIP_R350,
- CHIP_RV350,
- CHIP_RV380,
- CHIP_R420,
- CHIP_R423,
- CHIP_RV410,
- CHIP_RS400,
- CHIP_RS480,
- CHIP_RS600,
- CHIP_RS690,
- CHIP_RS740,
- CHIP_RV515,
- CHIP_R520,
- CHIP_RV530,
- CHIP_RV560,
- CHIP_RV570,
- CHIP_R580,
- CHIP_R600,
- CHIP_RV610,
- CHIP_RV630,
- CHIP_RV670,
- CHIP_RV620,
- CHIP_RV635,
- CHIP_RS780,
- CHIP_RS880,
- CHIP_RV770,
- CHIP_RV730,
- CHIP_RV710,
- CHIP_RV740,
- CHIP_CEDAR,
- CHIP_REDWOOD,
- CHIP_JUNIPER,
- CHIP_CYPRESS,
- CHIP_HEMLOCK,
- CHIP_LAST,
-};
-
-enum chip_class {
- R600,
- R700,
- EVERGREEN,
-};
-
-enum {
- R600_SHADER_PS = 1,
- R600_SHADER_VS,
- R600_SHADER_GS,
- R600_SHADER_FS,
- R600_SHADER_MAX = R600_SHADER_FS,
-};
-
-enum radeon_family radeon_get_family(struct radeon *rw);
-enum chip_class radeon_get_family_class(struct radeon *radeon);
-void radeon_set_mem_constant(struct radeon *radeon, boolean state);
-
-/* lowlevel WS bo */
-struct radeon_ws_bo;
-struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
- unsigned size, unsigned alignment, unsigned usage);
-struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
- unsigned handle);
-void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
-void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
-void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
- struct radeon_ws_bo *src);
-
-struct radeon_stype_info;
-
-/* currently limited to max buffers in a cb flush */
-#define RADEON_STATE_MAX_BO 8
-/*
- * states functions
- */
-struct radeon_state {
- struct radeon *radeon;
- unsigned refcount;
- struct radeon_stype_info *stype;
- unsigned state_id;
- unsigned id;
- unsigned shader_index;
- unsigned nstates;
- u32 states[64];
- unsigned npm4;
- unsigned cpm4;
- u32 pm4_crc;
- u32 pm4[128];
- unsigned nbo;
- struct radeon_ws_bo *bo[RADEON_STATE_MAX_BO];
- unsigned nreloc;
- unsigned reloc_pm4_id[8];
- unsigned reloc_bo_id[8];
- u32 placement[8];
- unsigned bo_dirty[4];
-};
-
-int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
-void radeon_state_fini(struct radeon_state *state);
-int radeon_state_pm4(struct radeon_state *state);
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
-
-/*
- * draw functions
- */
-struct radeon_draw {
- struct radeon *radeon;
- struct radeon_state **state;
-};
-
-int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
-void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
-void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
-
-/*
- * radeon context functions
- */
-#pragma pack(1)
-struct radeon_cs_reloc {
- uint32_t handle;
- uint32_t read_domain;
- uint32_t write_domain;
- uint32_t flags;
-};
-#pragma pack()
-
-struct radeon_ctx;
-
-struct radeon_ctx *radeon_ctx_init(struct radeon *radeon);
-void radeon_ctx_fini(struct radeon_ctx *ctx);
-void radeon_ctx_clear(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-
-/*
- * R600/R700
- */
-
-enum r600_stype {
- R600_STATE_CONFIG,
- R600_STATE_CB_CNTL,
- R600_STATE_RASTERIZER,
- R600_STATE_VIEWPORT,
- R600_STATE_SCISSOR,
- R600_STATE_BLEND,
- R600_STATE_DSA,
- R600_STATE_SHADER, /* has PS,VS,GS,FS variants */
- R600_STATE_CONSTANT, /* has PS,VS,GS,FS variants */
- R600_STATE_CBUF, /* has PS,VS,GS,FS variants */
- R600_STATE_RESOURCE, /* has PS,VS,GS,FS variants */
- R600_STATE_SAMPLER, /* has PS,VS,GS,FS variants */
- R600_STATE_SAMPLER_BORDER, /* has PS,VS,GS,FS variants */
- R600_STATE_CB0,
- R600_STATE_CB1,
- R600_STATE_CB2,
- R600_STATE_CB3,
- R600_STATE_CB4,
- R600_STATE_CB5,
- R600_STATE_CB6,
- R600_STATE_CB7,
- R600_STATE_DB,
- R600_STATE_QUERY_BEGIN,
- R600_STATE_QUERY_END,
- R600_STATE_UCP,
- R600_STATE_VGT,
- R600_STATE_DRAW,
- R600_STATE_CB_FLUSH,
- R600_STATE_DB_FLUSH,
- R600_STATE_MAX,
-};
-
-#include "r600_states_inc.h"
-#include "eg_states_inc.h"
-
-/* R600 QUERY BEGIN/END */
-#define R600_QUERY__OFFSET 0
-#define R600_QUERY_SIZE 1
-#define R600_QUERY_PM4 128
-
-#endif
#include <pipebuffer/pb_bufmgr.h>
#include "r600_priv.h"
-struct radeon_bo {
- struct pipe_reference reference;
- unsigned handle;
- unsigned size;
- unsigned alignment;
- unsigned map_count;
- void *data;
-};
-
-struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
-
struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
#include "util/u_inlines.h"
#include "util/u_debug.h"
#include <pipebuffer/pb_bufmgr.h>
-#include "radeon_priv.h"
+#include "r600.h"
+#include "r600_priv.h"
#include "r600_drm_public.h"
#include "xf86drm.h"
#include "radeon_drm.h"
#include <stdint.h>
#include <stdlib.h>
#include <assert.h>
+#include <pipebuffer/pb_bufmgr.h>
#include "r600.h"
unsigned flush_flags;
};
+struct radeon_bo {
+ struct pipe_reference reference;
+ unsigned handle;
+ unsigned size;
+ unsigned alignment;
+ unsigned map_count;
+ void *data;
+};
+
+struct radeon_ws_bo {
+ struct pipe_reference reference;
+ struct pb_buffer *pb;
+};
+
+
/* radeon_pciid.c */
unsigned radeon_family_from_device(unsigned device);
+/* r600_drm.c */
+struct radeon *radeon_decref(struct radeon *radeon);
+
+/* radeon_bo.c */
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
+void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo);
+struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
+ unsigned size, unsigned alignment, void *ptr);
+int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
+ struct radeon_bo *src);
+int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
+int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain);
+
+/* radeon_bo_pb.c */
+struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr,
+ uint32_t handle);
+
+/* radeon_ws_bo.c */
+unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *bo);
+unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *bo);
+
#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255)
#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1))
-
static void inline r600_context_reg(struct r600_context *ctx,
unsigned offset, unsigned value,
unsigned mask)
block->status |= R600_BLOCK_STATUS_DIRTY;
}
-struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
-void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo);
-
-struct radeon_ws_bo {
- struct pipe_reference reference;
- struct pb_buffer *pb;
-};
-
static inline void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
{
struct radeon_bo *bo;
#define GROUP_FORCE_NEW_BLOCK 0
-struct radeon_bo {
- struct pipe_reference reference;
- unsigned handle;
- unsigned size;
- unsigned alignment;
- unsigned map_count;
- void *data;
-};
int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
void radeon_bo_reference(struct radeon *radeon,
struct drm_radeon_cs drmib;
struct drm_radeon_cs_chunk chunks[2];
uint64_t chunk_array[2];
- struct r600_block *block;
int r;
if (!ctx->pm4_cdwords)
#include <string.h>
#include <sys/mman.h>
#include <errno.h>
-#include "radeon_priv.h"
+#include "r600_priv.h"
#include "xf86drm.h"
#include "radeon_drm.h"
-#include "radeon_priv.h"
-
-#include "util/u_inlines.h"
-#include "util/u_memory.h"
-#include "util/u_double_list.h"
-#include "pipebuffer/pb_buffer.h"
-#include "pipebuffer/pb_bufmgr.h"
+/*
+ * Copyright 2010 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie
+ */
+#include <util/u_inlines.h>
+#include <util/u_memory.h>
+#include <util/u_double_list.h>
+#include <pipebuffer/pb_buffer.h>
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
struct radeon_bo_pb {
struct pb_buffer b;
* Jerome Glisse
*/
#include <stdlib.h>
-#include "radeon_priv.h"
+#include "r600.h"
struct pci_id {
unsigned vendor;
+++ /dev/null
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef RADEON_PRIV_H
-#define RADEON_PRIV_H
-
-#include <stdint.h>
-#include "xf86drm.h"
-#include "xf86drmMode.h"
-#include <errno.h>
-#include "radeon.h"
-
-#include "pipe/p_compiler.h"
-#include "util/u_inlines.h"
-#include "pipe/p_defines.h"
-
-struct radeon;
-struct radeon_ctx;
-
-
-/*
- * radeon functions
- */
-typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
-struct radeon_register {
- unsigned offset;
- unsigned need_reloc;
- unsigned bo_id;
- char name[64];
-};
-
-struct radeon_bo {
- struct pipe_reference reference;
- unsigned handle;
- unsigned size;
- unsigned alignment;
- unsigned map_count;
- void *data;
-};
-
-struct radeon_sub_type {
- int shader_type;
- const struct radeon_register *regs;
- unsigned nstates;
-};
-
-struct radeon_stype_info {
- unsigned stype;
- unsigned num;
- unsigned stride;
- radeon_state_pm4_t pm4;
- struct radeon_sub_type reginfo[R600_SHADER_MAX];
- unsigned base_id;
- unsigned npm4;
-};
-
-struct radeon_ctx {
- struct radeon *radeon;
- u32 *pm4;
- int cdwords;
- int ndwords;
- unsigned nreloc;
- struct radeon_cs_reloc *reloc;
- unsigned nbo;
- struct radeon_bo **bo;
-};
-
-struct radeon {
- int fd;
- int refcount;
- unsigned device;
- unsigned family;
- enum chip_class chip_class;
- boolean use_mem_constant; /* true for evergreen */
- struct pb_manager *mman; /* malloc manager */
- struct pb_manager *kman; /* kernel bo manager */
- struct pb_manager *cman; /* cached bo manager */
- unsigned nstype;
- struct radeon_stype_info *stype;
- unsigned max_states;
-};
-
-struct radeon_ws_bo {
- struct pipe_reference reference;
- struct pb_buffer *pb;
-};
-
-extern struct radeon *radeon_new(int fd, unsigned device);
-extern struct radeon *radeon_incref(struct radeon *radeon);
-extern struct radeon *radeon_decref(struct radeon *radeon);
-extern unsigned radeon_family_from_device(unsigned device);
-extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
-
-/*
- * r600/r700 context functions
- */
-extern int r600_init(struct radeon *radeon);
-extern int r600_ctx_draw(struct radeon_ctx *ctx);
-extern int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc);
-
-/*
- * radeon state functions
- */
-extern u32 radeon_state_register_get(struct radeon_state *state, unsigned offset);
-extern int radeon_state_register_set(struct radeon_state *state, unsigned offset, u32 value);
-extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
-extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
-extern int radeon_state_pm4_generic(struct radeon_state *state);
-extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
-
-/*
- * radeon draw functions
- */
-extern int radeon_draw_pm4(struct radeon_draw *draw);
-
-/* ws bo winsys only */
-unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *bo);
-unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *bo);
-
-/* bo */
-struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
- unsigned size, unsigned alignment, void *ptr);
-int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
-void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
-void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
- struct radeon_bo *src);
-int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
-int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain);
-
-/* pipebuffer kernel bo manager */
-struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon);
-struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
-void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr);
-struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr,
- uint32_t handle);
-
-#endif
+/*
+ * Copyright 2010 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie
+ */
#include <pipe/p_compiler.h>
#include <pipe/p_screen.h>
#include <pipebuffer/pb_bufmgr.h>
-#include "radeon_priv.h"
+#include "r600_priv.h"
struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
unsigned size, unsigned alignment, unsigned usage)
projects / platform / upstream / mesa.git / commitdiff