&power_regs->hw_power_vddactrl);
}
-void mxs_mem_setup_vddd(void)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
- writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
- (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
- POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
- &power_regs->hw_power_vdddctrl);
-}
-
uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- mxs_mem_setup_vddd();
-
early_delay(10000);
mxs_mem_setup_cpu_and_hbus();
mxs_enable_output_rail_protection();
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
- mxs_power_set_vddx(&mxs_vddd_cfg, 1350, 1200);
+ mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |