drm/nv50-/disp: audit and version SOR_HDA_ELD method

The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
index a19e7d7..8b4e06a 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
@@ -22,25 +22,37 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/os.h>
-#include <core/class.h>
+#include <core/client.h>
+#include <nvif/unpack.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
 int
-nva3_hda_eld(struct nv50_disp_priv *priv, int or, u8 *data, u32 size)
+nva3_hda_eld(NV50_DISP_MTHD_V1)
 {
-       const u32 soff = (or * 0x800);
-       int i;
+       union {
+               struct nv50_disp_sor_hda_eld_v0 v0;
+       } *args = data;
+       const u32 soff = outp->or * 0x800;
+       int ret, i;
 
-       if (data && data[0]) {
+       nv_ioctl(object, "disp sor hda eld size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, true)) {
+               nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
+               if (size > 0x60)
+                       return -E2BIG;
+       } else
+               return ret;
+
+       if (size && args->v0.data[0]) {
                for (i = 0; i < size; i++)
-                       nv_wr32(priv, 0x61c440 + soff, (i << 8) | data[i]);
+                       nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
                for (; i < 0x60; i++)
                        nv_wr32(priv, 0x61c440 + soff, (i << 8));
                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003);
        } else
-       if (data) {
+       if (size) {
                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000001);
        } else {
                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000);

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
index 7176393..baf558f 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
@@ -22,8 +22,9 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/os.h>
-#include <core/class.h>
+#include <core/client.h>
+#include <nvif/unpack.h>
+#include <nvif/class.h>
 
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
@@ -33,19 +34,30 @@
 #include "nv50.h"
 
 int
-nvd0_hda_eld(struct nv50_disp_priv *priv, int or, u8 *data, u32 size)
+nvd0_hda_eld(NV50_DISP_MTHD_V1)
 {
-       const u32 soff = (or * 0x030);
-       int i;
+       union {
+               struct nv50_disp_sor_hda_eld_v0 v0;
+       } *args = data;
+       const u32 soff = outp->or * 0x030;
+       int ret, i;
 
-       if (data && data[0]) {
+       nv_ioctl(object, "disp sor hda eld size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, true)) {
+               nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
+               if (size > 0x60)
+                       return -E2BIG;
+       } else
+               return ret;
+
+       if (size && args->v0.data[0]) {
                for (i = 0; i < size; i++)
-                       nv_wr32(priv, 0x10ec00 + soff, (i << 8) | data[i]);
+                       nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
                for (; i < 0x60; i++)
                        nv_wr32(priv, 0x10ec00 + soff, (i << 8));
                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003);
        } else
-       if (data) {
+       if (size) {
                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000001);
        } else {
                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000);

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 869789f..9381b16 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -905,6 +905,10 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
                return priv->dac.sense(object, priv, data, size, head, outp);
        case NV50_DISP_MTHD_V1_SOR_PWR:
                return priv->sor.power(object, priv, data, size, head, outp);
+       case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
+               if (!priv->sor.hda_eld)
+                       return -ENODEV;
+               return priv->sor.hda_eld(object, priv, data, size, head, outp);
        default:
                break;
        }

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index ea9f37d..a09875f 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -47,7 +47,7 @@ struct nv50_disp_priv {
        struct {
                int nr;
                int (*power)(NV50_DISP_MTHD_V1);
-               int (*hda_eld)(struct nv50_disp_priv *, int sor, u8 *, u32);
+               int (*hda_eld)(NV50_DISP_MTHD_V1);
                int (*hdmi)(struct nv50_disp_priv *, int head, int sor, u32);
                u32 lvdsconf;
        } sor;
@@ -70,8 +70,8 @@ int nv50_dac_sense(NV50_DISP_MTHD_V1);
 
 #define SOR_MTHD(n) (n), (n) + 0x3f
 
-int nva3_hda_eld(struct nv50_disp_priv *, int, u8 *, u32);
-int nvd0_hda_eld(struct nv50_disp_priv *, int, u8 *, u32);
+int nva3_hda_eld(NV50_DISP_MTHD_V1);
+int nvd0_hda_eld(NV50_DISP_MTHD_V1);
 
 int nv84_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
 int nva3_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 92a54bd..ca42d79 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -46,7 +46,6 @@ nva3_disp_sclass[] = {
 static struct nouveau_omthds
 nva3_disp_base_omthds[] = {
        { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
-       { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD)     , nv50_sor_mthd },
        { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
        { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
        { SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 27c9e9e..77fe8cc 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -712,7 +712,6 @@ nvd0_disp_base_ofuncs = {
 struct nouveau_omthds
 nvd0_disp_base_omthds[] = {
        { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nvd0_disp_base_scanoutpos },
-       { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD)     , nv50_sor_mthd },
        { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
        { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
        { SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 16b19d4..be7e235 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -84,9 +84,6 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
        }
 
        switch (mthd & ~0x3f) {
-       case NVA3_DISP_SOR_HDA_ELD:
-               ret = priv->sor.hda_eld(priv, or, args, size);
-               break;
        case NV84_DISP_SOR_HDMI_PWR:
                ret = priv->sor.hdmi(priv, head, or, data);
                break;

diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index 98733df..234e117 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -59,7 +59,6 @@ struct nv04_display_scanoutpos {
 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
 
-#define NVA3_DISP_SOR_HDA_ELD                                        0x00010100
 #define NV84_DISP_SOR_HDMI_PWR                                       0x00012000
 #define NV84_DISP_SOR_HDMI_PWR_STATE                                 0x40000000
 #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF                             0x00000000

diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index dc7f63f..543ddb9 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1670,16 +1670,25 @@ nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        struct nouveau_connector *nv_connector;
        struct nv50_disp *disp = nv50_disp(encoder->dev);
+       struct {
+               struct nv50_disp_mthd_v1 base;
+               struct nv50_disp_sor_hda_eld_v0 eld;
+               u8 data[sizeof(nv_connector->base.eld)];
+       } args = {
+               .base.version = 1,
+               .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
+               .base.hasht   = nv_encoder->dcb->hasht,
+               .base.hashm   = nv_encoder->dcb->hashm,
+       };
 
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
        if (!drm_detect_monitor_audio(nv_connector->edid))
                return;
 
        drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
+       memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 
-       nvif_exec(disp->disp, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
-                             nv_connector->base.eld,
-                             nv_connector->base.eld[2] * 4);
+       nvif_mthd(disp->disp, 0, &args, sizeof(args));
 }
 
 static void
@@ -1687,8 +1696,17 @@ nv50_audio_disconnect(struct drm_encoder *encoder)
 {
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        struct nv50_disp *disp = nv50_disp(encoder->dev);
+       struct {
+               struct nv50_disp_mthd_v1 base;
+               struct nv50_disp_sor_hda_eld_v0 eld;
+       } args = {
+               .base.version = 1,
+               .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
+               .base.hasht   = nv_encoder->dcb->hasht,
+               .base.hashm   = nv_encoder->dcb->hashm,
+       };
 
-       nvif_exec(disp->disp, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
+       nvif_mthd(disp->disp, 0, &args, sizeof(args));
 }
 
 /******************************************************************************

diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index 4afc264..84d2926 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -346,4 +346,10 @@ struct nv50_disp_sor_pwr_v0 {
        __u8  pad02[6];
 };
 
+struct nv50_disp_sor_hda_eld_v0 {
+       __u8  version;
+       __u8  pad01[7];
+       __u8  data[];
+};
+
 #endif