u32 val;
int ret = 0;
+ /* K2G display controller does not support soft reset */
+ if (dispc->feat->subrev == DISPC_K2G)
+ return 0;
+
/* Soft reset */
REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
/* Wait for reset to complete */
of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
&dispc->memory_bandwidth_limit);
- /* K2G display controller does not support soft reset */
- if (feat->subrev != DISPC_K2G) {
- r = dispc_softreset(dispc);
- if (r)
- return r;
- }
+ r = dispc_softreset(dispc);
+ if (r)
+ return r;
tidss->dispc = dispc;