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arm64: dts: qcom: sc7280: Fixup the cpufreq node
author
Sibi Sankar
<sibis@codeaurora.org>
Thu, 29 Jul 2021 18:04:44 +0000
(23:34 +0530)
committer
Bjorn Andersson
<bjorn.andersson@linaro.org>
Thu, 5 Aug 2021 15:27:34 +0000
(10:27 -0500)
Fixup the register regions used by the cpufreq node on SC7280 SoC to
support per core L3 DCVS.
Fixes:
7dbd121a2c58
("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link:
https://lore.kernel.org/r/1627581885-32165-4-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm64/boot/dts/qcom/sc7280.dtsi
patch
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diff --git
a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index
b5a5685
..
dbbeb3a
100644
(file)
--- a/
arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/
arch/arm64/boot/dts/qcom/sc7280.dtsi
@@
-1795,9
+1795,9
@@
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
- reg = <0 0x18591
000 0 0x10
00>,
- <0 0x18592
000 0 0x10
00>,
- <0 0x18593
000 0 0x10
00>;
+ reg = <0 0x18591
100 0 0x9
00>,
+ <0 0x18592
100 0 0x9
00>,
+ <0 0x18593
100 0 0x9
00>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;