[AMDGPU] Add test case for a VOPD s_delay_alu insertion bug

diff --git a/llvm/test/CodeGen/AMDGPU/vopd-fmac-delay.mir b/llvm/test/CodeGen/AMDGPU/vopd-fmac-delay.mir
new file mode 100644 (file)
index 0000000..e1f1d45
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/vopd-fmac-delay.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=gcn-create-vopd,amdgpu-insert-delay-alu %s -o - | FileCheck %s
+
+# FIXME: Second VOPD pair reads vgpr0 and vgpr1 written by first pair, so there
+# should be a delay.
+---
+name: vopd_fmac_fmac
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vopd_fmac_fmac
+    ; CHECK: $vgpr0 = IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr2 = IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr4 = IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr3, $vgpr4, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr3, $vgpr4, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    $vgpr0 = IMPLICIT_DEF
+    $vgpr1 = IMPLICIT_DEF
+    $vgpr2 = IMPLICIT_DEF
+    $vgpr3 = IMPLICIT_DEF
+    $vgpr4 = IMPLICIT_DEF
+    $vgpr0 = V_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr0, implicit $mode, implicit $exec
+    $vgpr1 = V_FMAC_F32_e32 $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec
+    $vgpr0 = V_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr0, implicit $mode, implicit $exec
+    $vgpr1 = V_FMAC_F32_e32 $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec
+...