blend_state.logicOpEnable = state->blend_state->logicop_enable;
blend_state.logicOp = state->blend_state->logicop_func;
}
- if (screen->info.have_EXT_rasterization_order_attachment_access &&
- prog->nir[MESA_SHADER_FRAGMENT]->info.fs.uses_fbfetch_output)
+ if (state->rast_attachment_order)
blend_state.flags |= VK_PIPELINE_COLOR_BLEND_STATE_CREATE_RASTERIZATION_ORDER_ATTACHMENT_ACCESS_BIT_EXT;
VkPipelineMultisampleStateCreateInfo ms_state = {0};
VkPipelineColorBlendStateCreateInfo blend_state = {0};
blend_state.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO;
+ if (state->rast_attachment_order)
+ blend_state.flags |= VK_PIPELINE_COLOR_BLEND_STATE_CREATE_RASTERIZATION_ORDER_ATTACHMENT_ACCESS_BIT_EXT;
blend_state.attachmentCount = state->rendering_info.colorAttachmentCount;
if (state->blend_state)
blend_state.logicOp = state->blend_state->logicop_func;
}
}
zink_update_fs_key_samples(ctx);
+ if (zink_screen(pctx->screen)->info.have_EXT_rasterization_order_attachment_access) {
+ if (ctx->gfx_pipeline_state.rast_attachment_order != nir->info.fs.uses_fbfetch_output)
+ ctx->gfx_pipeline_state.dirty = true;
+ ctx->gfx_pipeline_state.rast_attachment_order = nir->info.fs.uses_fbfetch_output;
+ }
}
zink_update_fbfetch(ctx);
}
struct zink_gfx_pipeline_state {
/* order matches zink_gfx_output_key */
unsigned force_persample_interp:1;
- uint32_t rast_samples:7; //1 extra bit
+ uint32_t rast_samples:6;
uint32_t min_samples:6;
uint32_t feedback_loop : 1;
uint32_t feedback_loop_zs : 1;
+ uint32_t rast_attachment_order : 1;
uint32_t rp_state : 16;
VkSampleMask sample_mask;
uint32_t blend_id;
union {
struct {
unsigned force_persample_interp:1;
- uint32_t rast_samples:7; //1 extra bit
+ uint32_t rast_samples:6;
uint32_t min_samples:6;
uint32_t feedback_loop : 1;
uint32_t feedback_loop_zs : 1;
+ uint32_t rast_attachment_order : 1;
uint32_t rp_state : 16;
};
uint32_t key;