The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
if (ret)
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
- return ret;
+ clk.dev = NULL;
ret = clk_get_by_name(dev, "nand_x", &clk_x);
if (ret)
if (ret)
clk_ecc.dev = NULL;
- ret = clk_enable(&clk);
- if (ret)
- return ret;
+ if (clk.dev) {
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+ }
if (clk_x.dev) {
ret = clk_enable(&clk_x);