* config/i386/i386.md: Move some insn patterns around.

From-SVN: r242809

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index feb66fd..4d7bcfe 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6738,19 +6738,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*add<mode>3_cconly_overflow_2"
-  [(set (reg:CCC FLAGS_REG)
-       (compare:CCC
-         (plus:SWI
-           (match_operand:SWI 1 "nonimmediate_operand" "%0")
-           (match_operand:SWI 2 "<general_operand>" "<g>"))
-         (match_dup 2)))
-   (clobber (match_scratch:SWI 0 "=<r>"))]
-  "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "<MODE>")])
-
 (define_insn "*add<mode>3_cc_overflow_1"
   [(set (reg:CCC FLAGS_REG)
        (compare:CCC
@@ -6765,20 +6752,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*add<mode>3_cc_overflow_2"
-  [(set (reg:CCC FLAGS_REG)
-       (compare:CCC
-           (plus:SWI
-               (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-               (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
-           (match_dup 2)))
-   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
-       (plus:SWI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
-  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "<MODE>")])
-
 (define_insn "*addsi3_zext_cc_overflow_1"
   [(set (reg:CCC FLAGS_REG)
        (compare:CCC
@@ -6793,6 +6766,33 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
+(define_insn "*add<mode>3_cconly_overflow_2"
+  [(set (reg:CCC FLAGS_REG)
+       (compare:CCC
+         (plus:SWI
+           (match_operand:SWI 1 "nonimmediate_operand" "%0")
+           (match_operand:SWI 2 "<general_operand>" "<g>"))
+         (match_dup 2)))
+   (clobber (match_scratch:SWI 0 "=<r>"))]
+  "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*add<mode>3_cc_overflow_2"
+  [(set (reg:CCC FLAGS_REG)
+       (compare:CCC
+           (plus:SWI
+               (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
+               (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
+           (match_dup 2)))
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+       (plus:SWI (match_dup 1) (match_dup 2)))]
+  "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+  "add{<imodesuffix>}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "*addsi3_zext_cc_overflow_2"
   [(set (reg:CCC FLAGS_REG)
        (compare:CCC
@@ -7337,19 +7337,19 @@
    (set_attr "bdver1_decode" "direct")
    (set_attr "mode" "DI")])
 
-(define_insn "*<s>mulsi3_highpart_1"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (truncate:SI
+(define_insn "*<s>mulsi3_highpart_zext"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+       (zero_extend:DI (truncate:SI
          (lshiftrt:DI
-           (mult:DI
-             (any_extend:DI
-               (match_operand:SI 1 "nonimmediate_operand" "%a"))
-             (any_extend:DI
-               (match_operand:SI 2 "nonimmediate_operand" "rm")))
-           (const_int 32))))
+           (mult:DI (any_extend:DI
+                      (match_operand:SI 1 "nonimmediate_operand" "%a"))
+                    (any_extend:DI
+                      (match_operand:SI 2 "nonimmediate_operand" "rm")))
+           (const_int 32)))))
    (clobber (match_scratch:SI 3 "=1"))
    (clobber (reg:CC FLAGS_REG))]
-  "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "TARGET_64BIT
+   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "<sgnprefix>mul{l}\t%2"
   [(set_attr "type" "imul")
    (set_attr "length_immediate" "0")
@@ -7361,19 +7361,19 @@
    (set_attr "bdver1_decode" "direct")
    (set_attr "mode" "SI")])
 
-(define_insn "*<s>mulsi3_highpart_zext"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-       (zero_extend:DI (truncate:SI
+(define_insn "*<s>mulsi3_highpart_1"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+       (truncate:SI
          (lshiftrt:DI
-           (mult:DI (any_extend:DI
-                      (match_operand:SI 1 "nonimmediate_operand" "%a"))
-                    (any_extend:DI
-                      (match_operand:SI 2 "nonimmediate_operand" "rm")))
-           (const_int 32)))))
+           (mult:DI
+             (any_extend:DI
+               (match_operand:SI 1 "nonimmediate_operand" "%a"))
+             (any_extend:DI
+               (match_operand:SI 2 "nonimmediate_operand" "rm")))
+           (const_int 32))))
    (clobber (match_scratch:SI 3 "=1"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "<sgnprefix>mul{l}\t%2"
   [(set_attr "type" "imul")
    (set_attr "length_immediate" "0")
@@ -8217,6 +8217,18 @@
        (const_string "*")))
    (set_attr "mode" "SI,DI,DI,SI,DI")])
 
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*andsi_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+                 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
+  "and{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_insn "*andsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
        (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm,k")
@@ -8248,18 +8260,6 @@
    (set_attr "length_immediate" "*,*,0,0")
    (set_attr "mode" "SI")])
 
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*andsi_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
-  "and{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
 (define_insn "*andhi_1"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
        (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm,k")
@@ -8514,6 +8514,21 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI,DI,DI")])
 
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*andsi_2_zext"
+  [(set (reg FLAGS_REG)
+       (compare (and:SI
+                 (match_operand:SI 1 "nonimmediate_operand" "%0")
+                 (match_operand:SI 2 "x86_64_general_operand" "rme"))
+                (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (AND, SImode, operands)"
+  "and{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_insn "*andqi_2_maybe_si"
   [(set (reg FLAGS_REG)
        (compare (and:QI
@@ -8552,21 +8567,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*andsi_2_zext"
-  [(set (reg FLAGS_REG)
-       (compare (and:SI
-                 (match_operand:SI 1 "nonimmediate_operand" "%0")
-                 (match_operand:SI 2 "x86_64_general_operand" "rme"))
-                (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
-   && ix86_binary_operator_ok (AND, SImode, operands)"
-  "and{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
 (define_insn "*andqi_2_slp"
   [(set (reg FLAGS_REG)
        (compare (and:QI
@@ -8785,6 +8785,29 @@
   [(set_attr "type" "alu,alu,msklog")
    (set_attr "mode" "<MODE>")])
 
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*<code>si_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+        (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+                   (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+  "<logic>{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
+(define_insn "*<code>si_1_zext_imm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (any_or:DI
+        (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
+        (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+  "<logic>{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_insn "*<code>hi_1"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k")
        (any_or:HI
@@ -8818,29 +8841,6 @@
              (symbol_ref "!TARGET_PARTIAL_REG_STALL")]
           (symbol_ref "true")))])
 
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*<code>si_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-        (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                   (match_operand:SI 2 "x86_64_general_operand" "rme"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
-  "<logic>{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-(define_insn "*<code>si_1_zext_imm"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (any_or:DI
-        (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
-        (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
-  "<logic>{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
 (define_insn "*<code>qi_1_slp"
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
        (any_or:QI (match_dup 0)
@@ -8866,111 +8866,6 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "kxnor<mode>"
-  [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=r,!k")
-       (not:SWI1248_AVX512BW
-         (xor:SWI1248_AVX512BW
-           (match_operand:SWI1248_AVX512BW 1 "register_operand" "0,k")
-           (match_operand:SWI1248_AVX512BW 2 "register_operand" "r,k"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_AVX512F"
-{
-  if (which_alternative == 0)
-    return "#";
-
-  if (get_attr_mode (insn) == MODE_HI)
-    return "kxnorw\t{%2, %1, %0|%0, %1, %2}";
-  else
-    return "kxnor<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
-}
-  [(set_attr "type" "*,msklog")
-   (set_attr "prefix" "*,vex")
-   (set (attr "mode")
-     (cond [(and (eq_attr "alternative" "1")
-                (and (match_test "<MODE>mode == QImode")
-                     (not (match_test "TARGET_AVX512DQ"))))
-             (const_string "HI")
-          ]
-          (const_string "<MODE>")))])
-
-(define_split
-  [(set (match_operand:SWI1248x 0 "general_reg_operand")
-       (not:SWI1248x
-         (xor:SWI1248x
-           (match_dup 0)
-           (match_operand:SWI1248x 1 "general_reg_operand"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_AVX512F && reload_completed"
-   [(parallel [(set (match_dup 0)
-                   (xor:SWI1248x (match_dup 0)
-                                 (match_dup 1)))
-              (clobber (reg:CC FLAGS_REG))])
-    (set (match_dup 0)
-        (not:SWI1248x (match_dup 0)))])
-
-;;There are kortrest[bdq] but no intrinsics for them.
-;;We probably don't need to implement them.
-(define_insn "kortestzhi"
-  [(set (reg:CCZ FLAGS_REG)
-       (compare:CCZ
-         (ior:HI
-           (match_operand:HI 0 "register_operand" "k")
-           (match_operand:HI 1 "register_operand" "k"))
-         (const_int 0)))]
-  "TARGET_AVX512F && ix86_match_ccmode (insn, CCZmode)"
-  "kortestw\t{%1, %0|%0, %1}"
-  [(set_attr "mode" "HI")
-   (set_attr "type" "msklog")
-   (set_attr "prefix" "vex")])
-
-(define_insn "kortestchi"
-  [(set (reg:CCC FLAGS_REG)
-       (compare:CCC
-         (ior:HI
-           (match_operand:HI 0 "register_operand" "k")
-           (match_operand:HI 1 "register_operand" "k"))
-         (const_int -1)))]
-  "TARGET_AVX512F && ix86_match_ccmode (insn, CCCmode)"
-  "kortestw\t{%1, %0|%0, %1}"
-  [(set_attr "mode" "HI")
-   (set_attr "type" "msklog")
-   (set_attr "prefix" "vex")])
-
-(define_insn "kunpckhi"
-  [(set (match_operand:HI 0 "register_operand" "=k")
-       (ior:HI
-         (ashift:HI
-           (zero_extend:HI (match_operand:QI 1 "register_operand" "k"))
-           (const_int 8))
-         (zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))]
-  "TARGET_AVX512F"
-  "kunpckbw\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "mode" "HI")
-   (set_attr "type" "msklog")
-   (set_attr "prefix" "vex")])
-
-(define_insn "kunpcksi"
-  [(set (match_operand:SI 0 "register_operand" "=k")
-       (ior:SI
-         (ashift:SI
-           (zero_extend:SI (match_operand:HI 1 "register_operand" "k"))
-           (const_int 16))
-         (zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))]
-  "TARGET_AVX512BW"
-  "kunpckwd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "mode" "SI")])
-
-(define_insn "kunpckdi"
-  [(set (match_operand:DI 0 "register_operand" "=k")
-       (ior:DI
-         (ashift:DI
-           (zero_extend:DI (match_operand:SI 1 "register_operand" "k"))
-           (const_int 32))
-         (zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))]
-  "TARGET_AVX512BW"
-  "kunpckdq\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "mode" "DI")])
-
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 ;; ??? Special case for immediate operand is missing - it is tricky.
 (define_insn "*<code>si_2_zext"
@@ -9170,6 +9065,111 @@
    (set_attr "type" "alu")
    (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
+
+(define_insn "kxnor<mode>"
+  [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=r,!k")
+       (not:SWI1248_AVX512BW
+         (xor:SWI1248_AVX512BW
+           (match_operand:SWI1248_AVX512BW 1 "register_operand" "0,k")
+           (match_operand:SWI1248_AVX512BW 2 "register_operand" "r,k"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_AVX512F"
+{
+  if (which_alternative == 0)
+    return "#";
+
+  if (get_attr_mode (insn) == MODE_HI)
+    return "kxnorw\t{%2, %1, %0|%0, %1, %2}";
+  else
+    return "kxnor<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+}
+  [(set_attr "type" "*,msklog")
+   (set_attr "prefix" "*,vex")
+   (set (attr "mode")
+     (cond [(and (eq_attr "alternative" "1")
+                (and (match_test "<MODE>mode == QImode")
+                     (not (match_test "TARGET_AVX512DQ"))))
+             (const_string "HI")
+          ]
+          (const_string "<MODE>")))])
+
+(define_split
+  [(set (match_operand:SWI1248x 0 "general_reg_operand")
+       (not:SWI1248x
+         (xor:SWI1248x
+           (match_dup 0)
+           (match_operand:SWI1248x 1 "general_reg_operand"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_AVX512F && reload_completed"
+   [(parallel [(set (match_dup 0)
+                   (xor:SWI1248x (match_dup 0)
+                                 (match_dup 1)))
+              (clobber (reg:CC FLAGS_REG))])
+    (set (match_dup 0)
+        (not:SWI1248x (match_dup 0)))])
+
+;;There are kortrest[bdq] but no intrinsics for them.
+;;We probably don't need to implement them.
+(define_insn "kortestzhi"
+  [(set (reg:CCZ FLAGS_REG)
+       (compare:CCZ
+         (ior:HI
+           (match_operand:HI 0 "register_operand" "k")
+           (match_operand:HI 1 "register_operand" "k"))
+         (const_int 0)))]
+  "TARGET_AVX512F && ix86_match_ccmode (insn, CCZmode)"
+  "kortestw\t{%1, %0|%0, %1}"
+  [(set_attr "mode" "HI")
+   (set_attr "type" "msklog")
+   (set_attr "prefix" "vex")])
+
+(define_insn "kortestchi"
+  [(set (reg:CCC FLAGS_REG)
+       (compare:CCC
+         (ior:HI
+           (match_operand:HI 0 "register_operand" "k")
+           (match_operand:HI 1 "register_operand" "k"))
+         (const_int -1)))]
+  "TARGET_AVX512F && ix86_match_ccmode (insn, CCCmode)"
+  "kortestw\t{%1, %0|%0, %1}"
+  [(set_attr "mode" "HI")
+   (set_attr "type" "msklog")
+   (set_attr "prefix" "vex")])
+
+(define_insn "kunpckhi"
+  [(set (match_operand:HI 0 "register_operand" "=k")
+       (ior:HI
+         (ashift:HI
+           (zero_extend:HI (match_operand:QI 1 "register_operand" "k"))
+           (const_int 8))
+         (zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))]
+  "TARGET_AVX512F"
+  "kunpckbw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mode" "HI")
+   (set_attr "type" "msklog")
+   (set_attr "prefix" "vex")])
+
+(define_insn "kunpcksi"
+  [(set (match_operand:SI 0 "register_operand" "=k")
+       (ior:SI
+         (ashift:SI
+           (zero_extend:SI (match_operand:HI 1 "register_operand" "k"))
+           (const_int 16))
+         (zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))]
+  "TARGET_AVX512BW"
+  "kunpckwd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mode" "SI")])
+
+(define_insn "kunpckdi"
+  [(set (match_operand:DI 0 "register_operand" "=k")
+       (ior:DI
+         (ashift:DI
+           (zero_extend:DI (match_operand:SI 1 "register_operand" "k"))
+           (const_int 32))
+         (zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))]
+  "TARGET_AVX512BW"
+  "kunpckdq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mode" "DI")])
 \f
 ;; Negation instructions
 
@@ -9578,6 +9578,16 @@
    (set_attr "prefix" "*,vex")
    (set_attr "mode" "<MODE>")])
 
+;; ??? Currently never generated - xor is used instead.
+(define_insn "*one_cmplsi2_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (not:SI (match_operand:SI 1 "register_operand" "0"))))]
+  "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
+  "not{l}\t%k0"
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "SI")])
+
 (define_insn "*one_cmplhi2_1"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,!k")
        (not:HI (match_operand:HI 1 "nonimmediate_operand" "0,k")))]
@@ -9626,16 +9636,6 @@
              (symbol_ref "!TARGET_PARTIAL_REG_STALL")]
           (symbol_ref "true")))])
 
-;; ??? Currently never generated - xor is used instead.
-(define_insn "*one_cmplsi2_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-         (not:SI (match_operand:SI 1 "register_operand" "0"))))]
-  "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
-  "not{l}\t%k0"
-  [(set_attr "type" "negnot")
-   (set_attr "mode" "SI")])
-
 (define_insn "*one_cmpl<mode>2_2"
   [(set (reg FLAGS_REG)
        (compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
@@ -10442,35 +10442,35 @@
    (set_attr "modrm" "0,1")
    (set_attr "mode" "DI")])
 
-(define_insn "ashrsi3_cvt"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
-       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
-                    (match_operand:QI 2 "const_int_operand")))
+(define_insn "*ashrsi3_cvt_zext"
+  [(set (match_operand:DI 0 "register_operand" "=*d,r")
+       (zero_extend:DI
+         (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
+                      (match_operand:QI 2 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
-  "INTVAL (operands[2]) == 31
+  "TARGET_64BIT && INTVAL (operands[2]) == 31
    && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
    && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "@
    {cltd|cdq}
-   sar{l}\t{%2, %0|%0, %2}"
+   sar{l}\t{%2, %k0|%k0, %2}"
   [(set_attr "type" "imovx,ishift")
    (set_attr "prefix_0f" "0,*")
    (set_attr "length_immediate" "0,*")
    (set_attr "modrm" "0,1")
    (set_attr "mode" "SI")])
 
-(define_insn "*ashrsi3_cvt_zext"
-  [(set (match_operand:DI 0 "register_operand" "=*d,r")
-       (zero_extend:DI
-         (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
-                      (match_operand:QI 2 "const_int_operand"))))
+(define_insn "ashrsi3_cvt"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
+       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
+                    (match_operand:QI 2 "const_int_operand")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && INTVAL (operands[2]) == 31
+  "INTVAL (operands[2]) == 31
    && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
    && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "@
    {cltd|cdq}
-   sar{l}\t{%2, %k0|%k0, %2}"
+   sar{l}\t{%2, %0|%0, %2}"
   [(set_attr "type" "imovx,ishift")
    (set_attr "prefix_0f" "0,*")
    (set_attr "length_immediate" "0,*")