drm/amdgpu: add sriov nbio callback structure
authorHorace Chen <horace.chen@amd.com>
Thu, 21 Jul 2022 03:57:44 +0000 (11:57 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 1 Sep 2022 19:11:00 +0000 (15:11 -0400)
[Why]
under SR-IOV, the nbio doorbell range will be defined by PF. So VF
nbio doorbell range registers will be blocked. It will cause violation
if VF access those registers directly.

[How]
create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
skip the setting for the doorbell range registers.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h

index 5fd56eb..854ca8d 100644 (file)
@@ -2242,7 +2242,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case IP_VERSION(4, 3, 0):
        case IP_VERSION(4, 3, 1):
-               adev->nbio.funcs = &nbio_v4_3_funcs;
+               if (amdgpu_sriov_vf(adev))
+                       adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
+               else
+                       adev->nbio.funcs = &nbio_v4_3_funcs;
                adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
                break;
        case IP_VERSION(7, 7, 0):
index 982a89f..15eb365 100644 (file)
@@ -488,3 +488,47 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
        .get_rom_offset = nbio_v4_3_get_rom_offset,
        .program_aspm = nbio_v4_3_program_aspm,
 };
+
+
+static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev,
+                                       bool use_doorbell, int doorbell_index)
+{
+}
+
+static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+                                         bool use_doorbell, int doorbell_index,
+                                         int doorbell_size)
+{
+}
+
+static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
+                                        int doorbell_index, int instance)
+{
+}
+
+static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev)
+{
+}
+
+const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {
+       .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
+       .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
+       .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
+       .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
+       .get_rev_id = nbio_v4_3_get_rev_id,
+       .mc_access_enable = nbio_v4_3_mc_access_enable,
+       .get_memsize = nbio_v4_3_get_memsize,
+       .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range,
+       .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range,
+       .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init,
+       .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
+       .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture,
+       .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range,
+       .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating,
+       .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep,
+       .get_clockgating_state = nbio_v4_3_get_clockgating_state,
+       .ih_control = nbio_v4_3_ih_control,
+       .init_registers = nbio_v4_3_init_registers,
+       .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
+       .get_rom_offset = nbio_v4_3_get_rom_offset,
+};
index ade4366..711999c 100644 (file)
@@ -28,5 +28,6 @@
 
 extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg;
 extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs;
+extern const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs;
 
 #endif