OS << ", mu";
}
-bool isFaultFirstLoad(const MachineInstr &MI) {
- return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
- !MI.isInlineAsm();
-}
-
} // namespace llvm
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
-#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/RISCVISAInfo.h"
} // namespace RISCVVType
-bool isFaultFirstLoad(const MachineInstr &MI);
} // namespace llvm
#endif
}
void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
+ const MachineFunction *MF = MBB.getParent();
+ const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
+
for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++;
- if (isFaultFirstLoad(MI)) {
+ if (TII->isFaultFirstLoad(MI)) {
Register VLOutput = MI.getOperand(1).getReg();
if (!MRI->use_nodbg_empty(VLOutput))
BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
return std::make_pair(8u, 1u);
}
}
+
+bool RISCVInstrInfo::isFaultFirstLoad(const MachineInstr &MI) const {
+ return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
+ !MI.isInlineAsm();
+}
Optional<std::pair<unsigned, unsigned>>
isRVVSpillForZvlsseg(unsigned Opcode) const;
+ bool isFaultFirstLoad(const MachineInstr &MI) const;
+
protected:
const RISCVSubtarget &STI;
};
const TargetRegisterInfo *TRI =
MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
+ const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
+
assert(TRI && "TargetRegisterInfo expected");
uint64_t TSFlags = MI->getDesc().TSFlags;
if (RISCVII::hasSEWOp(TSFlags))
--NumOps;
- bool hasVLOutput = isFaultFirstLoad(*MI);
+ bool hasVLOutput = TII->isFaultFirstLoad(*MI);
for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
// Skip vl ouput. It should be the second output.