sh: Fix sh7264 clock speed and related serial setting

The generalised calculation of the serial bit rate reg also applies
to sh7264, it was just the clock speed that was set incorrectly.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 4e16e48..0b3e779 100644 (file)
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -686,8 +686,6 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_CPU_SH7264)
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif

diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index c1ffc34..af9524e 100644 (file)
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -65,7 +65,7 @@
 #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
 
 /* Board Clock */
-#define CONFIG_SYS_CLK_FREQ    33333333
+#define CONFIG_SYS_CLK_FREQ    36000000
 #define CMT_CLK_DIVIDER                32      /* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ          (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)