drm/radeon: implement UVD hw workarounds for R6xx v3

Only the essentials, cause this hw generation is really buggy.

v2: start supporting RV670,RV620 and RV635 as well
v3: activate more workarounds

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 420bed1..671b480 100644 (file)
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -330,6 +330,7 @@
 #define        HDP_TILING_CONFIG                               0x2F3C
 #define HDP_DEBUG1                                      0x2F34
 
+#define MC_CONFIG                                      0x2000
 #define MC_VM_AGP_TOP                                  0x2184
 #define MC_VM_AGP_BOT                                  0x2188
 #define        MC_VM_AGP_BASE                                  0x218C
@@ -375,6 +376,8 @@
 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                        0x2194
 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR             0x2198
 
+#define RS_DQ_RD_RET_CONF                              0x2348
+
 #define        PA_CL_ENHANCE                                   0x8A14
 #define                CLIP_VTX_REORDER_ENA                            (1 << 0)
 #define                NUM_CLIP_SEQ(x)                                 ((x) << 1)

diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 62d7086..c3e182b 100644 (file)
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -207,8 +207,32 @@ done:
        /* lower clocks again */
        radeon_set_uvd_clocks(rdev, 0, 0);
 
-       if (!r)
+       if (!r) {
+               switch (rdev->family) {
+               case CHIP_RV610:
+               case CHIP_RV630:
+               case CHIP_RV620:
+                       /* 64byte granularity workaround */
+                       WREG32(MC_CONFIG, 0);
+                       WREG32(MC_CONFIG, 1 << 4);
+                       WREG32(RS_DQ_RD_RET_CONF, 0x3f);
+                       WREG32(MC_CONFIG, 0x1f);
+
+                       /* fall through */
+               case CHIP_RV670:
+               case CHIP_RV635:
+
+                       /* write clean workaround */
+                       WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
+                       break;
+
+               default:
+                       /* TODO: Do we need more? */
+                       break;
+               }
+
                DRM_INFO("UVD initialized successfully.\n");
+       }
 
        return r;
 }