Add tests for OpFUnord with NaN
authorToni Merilehti <toni.merilehti@siru.fi>
Mon, 4 Mar 2019 11:43:39 +0000 (13:43 +0200)
committerAlexander Galazin <Alexander.Galazin@arm.com>
Fri, 22 Mar 2019 12:48:53 +0000 (08:48 -0400)
Add OpFUnord test cases that use NaN (not a number) values.
The functionality for testing NaN values is implemented
in commit acafd1d389d1d18d4e4410862d96064f9fca551e.

New tests:

dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.*

Components: Vulkan

VK-GL-CTS issue 1612

Change-Id: Ifd49c5ebe6382737cb0fb6ffca1a350889a54905

android/cts/master/vk-master.txt
external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp
external/vulkancts/mustpass/1.1.4/vk-default-no-waivers.txt
external/vulkancts/mustpass/1.1.4/vk-default.txt

index 752a010..fb3d980 100755 (executable)
@@ -224129,6 +224129,12 @@ dEQP-VK.spirv_assembly.instruction.compute.localsize.literal_localsize_z
 dEQP-VK.spirv_assembly.instruction.compute.localsize.literal_and_specid_localsize_z
 dEQP-VK.spirv_assembly.instruction.compute.localsize.specid_localsize_z
 dEQP-VK.spirv_assembly.instruction.compute.opnop.all
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.equal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.less
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.lessequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greater
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greaterequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.notequal
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iadd
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.isub
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iinc
index 1d25d90..3023827 100644 (file)
@@ -431,17 +431,17 @@ do { \
        cases.push_back(OpFUnordCase(#NAME, OPCODE, compare_##NAME::compare)); \
 } while (deGetFalse())
 
-tcu::TestCaseGroup* createOpFUnordGroup (tcu::TestContext& testCtx, const bool nanSupported)
+tcu::TestCaseGroup* createOpFUnordGroup (tcu::TestContext& testCtx, const bool testWithNan)
 {
-       const string                                    nan                             = nanSupported ? "_nan" : "";
+       const string                                    nan                             = testWithNan ? "_nan" : "";
        const string                                    groupName               = "opfunord" + nan;
        de::MovePtr<tcu::TestCaseGroup> group                   (new tcu::TestCaseGroup(testCtx, groupName.c_str(), "Test the OpFUnord* opcodes"));
        de::Random                                              rnd                             (deStringHash(group->getName()));
        const int                                               numElements             = 100;
        vector<OpFUnordCase>                    cases;
-       string                                                  extensions              = nanSupported ? "OpExtension \"SPV_KHR_float_controls\"\n" : "";
-       string                                                  capabilities    = nanSupported ? "OpCapability SignedZeroInfNanPreserve\n" : "";
-       string                          exeModes        = nanSupported ? "OpExecutionMode %main SignedZeroInfNanPreserve 32\n" : "";
+       string                                                  extensions              = testWithNan ? "OpExtension \"SPV_KHR_float_controls\"\n" : "";
+       string                                                  capabilities    = testWithNan ? "OpCapability SignedZeroInfNanPreserve\n" : "";
+       string                                                  exeModes                = testWithNan ? "OpExecutionMode %main SignedZeroInfNanPreserve 32\n" : "";
        const StringTemplate                    shaderTemplate  (
                string(getComputeAsmShaderPreamble(capabilities, extensions, exeModes)) +
                "OpSource GLSL 430\n"
@@ -534,13 +534,15 @@ tcu::TestCaseGroup* createOpFUnordGroup (tcu::TestContext& testCtx, const bool n
                spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
                spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
                spec.outputs.push_back(BufferSp(new Int32Buffer(expectedInts)));
-               spec.numWorkGroups = IVec3(numElements, 1, 1);
-               spec.verifyIO = nanSupported ? &compareFUnord<true> : &compareFUnord<false>;
-               if (nanSupported)
+               spec.numWorkGroups      = IVec3(numElements, 1, 1);
+               spec.verifyIO           = testWithNan ? &compareFUnord<true> : &compareFUnord<false>;
+
+               if (testWithNan)
                {
                        spec.extensions.push_back("VK_KHR_shader_float_controls");
                        spec.requestedVulkanFeatures.floatControlsProperties.shaderSignedZeroInfNanPreserveFloat32 = DE_TRUE;
                }
+
                group->addChild(new SpvAsmComputeShaderCase(testCtx, cases[caseNdx].name, cases[caseNdx].name, spec));
        }
 
@@ -18338,6 +18340,7 @@ tcu::TestCaseGroup* createInstructionTests (tcu::TestContext& testCtx)
        computeTests->addChild(createLocalSizeGroup(testCtx));
        computeTests->addChild(createOpNopGroup(testCtx));
        computeTests->addChild(createOpFUnordGroup(testCtx, TEST_WITHOUT_NAN));
+       computeTests->addChild(createOpFUnordGroup(testCtx, TEST_WITH_NAN));
        computeTests->addChild(createOpAtomicGroup(testCtx, false));
        computeTests->addChild(createOpAtomicGroup(testCtx, true));                                     // Using new StorageBuffer decoration
        computeTests->addChild(createOpAtomicGroup(testCtx, false, 1024, true));        // Return value validation
index 9d941b9..700f066 100644 (file)
@@ -224141,6 +224141,12 @@ dEQP-VK.spirv_assembly.instruction.compute.opfunord.lessequal
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.greater
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.greaterequal
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.notequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.equal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.less
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.lessequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greater
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greaterequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.notequal
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iadd
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.isub
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iinc
index 01b9602..6e9c896 100644 (file)
@@ -224141,6 +224141,12 @@ dEQP-VK.spirv_assembly.instruction.compute.opfunord.lessequal
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.greater
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.greaterequal
 dEQP-VK.spirv_assembly.instruction.compute.opfunord.notequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.equal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.less
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.lessequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greater
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.greaterequal
+dEQP-VK.spirv_assembly.instruction.compute.opfunord_nan.notequal
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iadd
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.isub
 dEQP-VK.spirv_assembly.instruction.compute.opatomic.iinc