phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Mon, 11 Sep 2023 20:07:14 +0000 (22:07 +0200)
committerVinod Koul <vkoul@kernel.org>
Thu, 21 Sep 2023 14:23:13 +0000 (16:23 +0200)
There are two instances of the POWER_STATE_CONFIG1 register: one in
the PCS space and another one in PCS_USB.

The downstream init sequence pokes the latter one while we've been poking
the former one (and misnamed it as the latter one, impostor!). Fix that
up to avoid UB.

Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550")
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-1-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h

index cbb28af..8fd240d 100644 (file)
@@ -859,10 +859,10 @@ static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
-       QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
 };
 
 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
        QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
index 9510e63..c38530d 100644 (file)
@@ -12,7 +12,7 @@
 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3            0xcc
 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6            0xd8
 #define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1             0xdc
-#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1       0x90
+#define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1            0x90
 #define QPHY_USB_V6_PCS_RX_SIGDET_LVL                  0x188
 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L           0x190
 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H           0x194
@@ -23,6 +23,7 @@
 #define QPHY_USB_V6_PCS_EQ_CONFIG1                     0x1dc
 #define QPHY_USB_V6_PCS_EQ_CONFIG5                     0x1ec
 
+#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1       0x00
 #define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL   0x18
 #define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2  0x3c
 #define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L                0x40