#ifndef R8192_HW
#define R8192_HW
-typedef enum _BaseBand_Config_Type {
- BaseBand_Config_PHY_REG = 0, //Radio Path A
- BaseBand_Config_AGC_TAB = 1, //Radio Path B
-} BaseBand_Config_Type, *PBaseBand_Config_Type;
#define RTL8187_REQT_READ 0xc0
#define RTL8187_REQT_WRITE 0x40
#define RTL8187_REQ_GET_REGS 0x05
* notice: BB parameters may change all the time, so please make
* sure it has been synced with the newest.
*****************************************************************************/
-static void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
+static void rtl8192_phyConfigBB(struct net_device *dev,
+ enum baseband_config_type ConfigType)
{
u32 i;
Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
}
#endif
- if (ConfigType == BaseBand_Config_PHY_REG) {
+ if (ConfigType == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i],
bMaskDWord,
i, Rtl8192UsbPHY_REG_1T2RArray[i],
Rtl8192UsbPHY_REG_1T2RArray[i+1]);
}
- } else if (ConfigType == BaseBand_Config_AGC_TAB) {
+ } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) {
for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i],
bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
/* ----BB Register Initilazation---- */
/* ==m==>Set PHY REG From Header<==m== */
- rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
+ rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG);
/* ----Set BB reset de-Active---- */
read_nic_dword(dev, CPU_GEN, ®_u32);
/* ----BB AGC table Initialization---- */
/* ==m==>Set PHY REG From Header<==m== */
- rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
+ rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB);
/* ----Enable XSTAL ---- */
write_nic_byte_E(dev, 0x5e, 0x00);