ENABLE_SCLK_PERIC, 12,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
- ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ ENABLE_SCLK_PERIC, 11,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
"ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
- 3, CLK_SET_RATE_PARENT, 0),
+ 3, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
ENABLE_SCLK_PERIC, 2,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),