gfx-display: restore hdmi dpll register

BZ: 37424

hdmi dpll register is missed, it needs restore. and dsi context is NULL if pipe
equals to 1, it will cause kernel ipanic.

Change-Id: Ic2d11bbc803af476138a514f5893a4c5514ab4bd
Signed-off-by: Geng Xiujun <xiujun.geng@intel.com>
Reviewed-on: http://android.intel.com:8080/49528
Reviewed-by: Zhang, Lei <lei.zhang@intel.com>
Reviewed-by: Ai, Ke <ke.ai@intel.com>
Tested-by: Tong, BoX <box.tong@intel.com>
Reviewed-by: Hu, Austin <austin.hu@intel.com>
Reviewed-by: Xu, Randy <randy.xu@intel.com>
Tested-by: Xu, Randy <randy.xu@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c
index e68db08..5a408cc 100644 (file)
--- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c
+++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c
@@ -2473,8 +2473,15 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
                /* Now start the DSI clock */
                REG_WRITE(MRST_DPLL_A, 0x0);
                REG_WRITE(MRST_FPA0, 0x0);
-               REG_WRITE(MRST_FPA0, ctx->fp);
-               REG_WRITE(MRST_DPLL_A, ((ctx->dpll) & ~BIT30));
+               if (ctx != NULL) {
+                       REG_WRITE(MRST_FPA0, ctx->fp);
+                       REG_WRITE(MRST_DPLL_A, ((ctx->dpll) & ~BIT30));
+               } else {
+                       pr_err("no dsi context, using hardcoded DPLL value\n");
+                       /* using hardcode DPLL */
+                       REG_WRITE(MRST_FPA0, 0xC1);
+                       REG_WRITE(MRST_DPLL_A, 0x00800000);
+               }
 
                /* per spec of display controller, before enable VCO, need wait
                 * 0.5us, here wait 1us */

diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c
index 8b5247b..928c9f2 100755 (executable)
--- a/drivers/staging/mrst/drv/psb_intel_display2.c
+++ b/drivers/staging/mrst/drv/psb_intel_display2.c
@@ -2314,8 +2314,10 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
        }
 
 #ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE
-       ctx->dpll = dpll;
-       ctx->fp = fp;
+       if (pipe == 0 && ctx != NULL) {
+               ctx->dpll = dpll;
+               ctx->fp = fp;
+       }
 #endif
 
        if (is_mipi) {

diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c
index c5b78d7..e6a278a 100644 (file)
--- a/drivers/staging/mrst/drv/psb_powermgmt.c
+++ b/drivers/staging/mrst/drv/psb_powermgmt.c
@@ -1220,7 +1220,6 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
        /*make sure VGA plane is off. it initializes to on after reset!*/
        PSB_WVDC32(0x80000000, VGACNTRL);
 
-#ifndef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE
        dpll = PSB_RVDC32(dpll_reg);
 
        if (!(dpll & DPLL_VCO_ENABLE)) {
@@ -1262,7 +1261,6 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
                        return -EINVAL;
                }
        }
-#endif
 
        /* Restore mode */
        PSB_WVDC32(htot_val, htot_reg);