[RISC-V] Fixed alias for addi x2, x2, 0

A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

llvm-svn: 339381

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 5d1c62c..eae9441 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -187,7 +187,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>,
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    return isShiftedInt<6, 4>(Imm);
+    return isShiftedInt<6, 4>(Imm) && (Imm != 0);
   }];
 }
 

diff --git a/llvm/test/MC/RISCV/rv32c-aliases-valid.s b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
index b743b3f..f9c07e2 100644 (file)
--- a/llvm/test/MC/RISCV/rv32c-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
@@ -60,3 +60,6 @@ li x12, -0x80000000
 li x12, 0x80000000
 # CHECK-EXPAND: c.li a2, -1
 li x12, 0xFFFFFFFF
+
+# CHECK-EXPAND: c.mv sp, sp
+addi x2, x2, 0