drm/amd/display: Fix wrong latency assignment for VEGA clock levels
authorHarry Wentland <harry.wentland@amd.com>
Tue, 29 May 2018 13:59:13 +0000 (09:59 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 29 May 2018 18:16:48 +0000 (13:16 -0500)
Also drop wrong 10kHz comment

Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

index ead3d21..d5e6b45 100644 (file)
@@ -256,9 +256,8 @@ static void pp_to_dc_clock_levels_with_latency(
 
        for (i = 0; i < clk_level_info->num_levels; i++) {
                DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-               /* translate 10kHz to kHz */
                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
-               clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz;
+               clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
        }
 }