info->max_tcc_blocks = device_info.num_tcc_blocks;
info->max_se = device_info.num_shader_engines;
info->max_sa_per_se = device_info.num_shader_arrays_per_engine;
+ info->num_cu_per_sh = device_info.num_cu_per_sh;
info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0;
info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0;
fprintf(f, " min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
fprintf(f, " max_se = %i\n", info->max_se);
fprintf(f, " max_sa_per_se = %i\n", info->max_sa_per_se);
+ fprintf(f, " num_cu_per_sh = %i\n", info->num_cu_per_sh);
fprintf(f, " max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
fprintf(f, " num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
fprintf(f, " num_physical_wave64_vgprs_per_simd = %i\n",
uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */
uint32_t max_se; /* number of shader engines incl. disabled ones */
uint32_t max_sa_per_se; /* shader arrays per shader engine */
+ uint32_t num_cu_per_sh;
uint32_t max_wave64_per_simd;
uint32_t num_physical_sgprs_per_simd;
uint32_t num_physical_wave64_vgprs_per_simd;