clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 99bcb7c..8e7bb43 100644 (file)
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_GEN3_Z("z",         R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
-       DEF_GEN3_Z("z2",        R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
+       DEF_GEN3_Z("z",         R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
+       DEF_GEN3_Z("z2",        R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
        DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index d4cf1c9..d09c0ab 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -74,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
-       DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
+       DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
+       DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
        DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 77254f2..7efd031 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -74,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
-       DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
+       DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
+       DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
        DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index f8f7355..fefa26a 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
        DEF_GEN3_OSC(".r",      CLK_RINT,               CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_GEN3_Z("z",         R8A77965_CLK_Z,         CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
+       DEF_GEN3_Z("z",         R8A77965_CLK_Z,         CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
        DEF_FIXED("ztr",        R8A77965_CLK_ZTR,       CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A77965_CLK_ZTRD2,     CLK_PLL1_DIV2,  12, 1),
        DEF_FIXED("zt",         R8A77965_CLK_ZT,        CLK_PLL1_DIV2,  4, 1),

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 1307119..8d51dbf 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -88,8 +88,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
 #define CPG_FRQCRB                     0x00000004
 #define CPG_FRQCRB_KICK                        BIT(31)
 #define CPG_FRQCRC                     0x000000e0
-#define CPG_FRQCRC_ZFC_MASK            GENMASK(12, 8)
-#define CPG_FRQCRC_Z2FC_MASK           GENMASK(4, 0)
 
 struct cpg_z_clk {
        struct clk_hw hw;
@@ -180,8 +178,8 @@ static const struct clk_ops cpg_z_clk_ops = {
 static struct clk * __init cpg_z_clk_register(const char *name,
                                              const char *parent_name,
                                              void __iomem *reg,
-                                             unsigned long mask,
-                                             unsigned int div)
+                                             unsigned int div,
+                                             unsigned int offset)
 {
        struct clk_init_data init;
        struct cpg_z_clk *zclk;
@@ -200,7 +198,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
        zclk->reg = reg + CPG_FRQCRC;
        zclk->kick_reg = reg + CPG_FRQCRB;
        zclk->hw.init = &init;
-       zclk->mask = mask;
+       zclk->mask = GENMASK(offset + 4, offset);
        zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
 
        clk = clk_register(NULL, &zclk->hw);
@@ -661,14 +659,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
                break;
 
        case CLK_TYPE_GEN3_Z:
-               return cpg_z_clk_register(core->name, __clk_get_name(parent),
-                                         base, CPG_FRQCRC_ZFC_MASK,
-                                         core->div);
-
        case CLK_TYPE_GEN3_Z2:
                return cpg_z_clk_register(core->name, __clk_get_name(parent),
-                                         base, CPG_FRQCRC_Z2FC_MASK,
-                                         core->div);
+                                         base, core->div, core->offset);
 
        case CLK_TYPE_GEN3_OSC:
                /*

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 8029366..9b4bb76 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -52,8 +52,8 @@ enum rcar_gen3_clk_types {
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,      \
                 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
 
-#define DEF_GEN3_Z(_name, _id, _type, _parent, _div)   \
-       DEF_BASE(_name, _id, _type, _parent, .div = _div)
+#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset)  \
+       DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
 
 struct rcar_gen3_cpg_pll_config {
        u8 extal_div;