drm/i915/selftests: Run the perf MI_BB tests on gen4/5

Now that we know the ring timestamp frequency on gen4/5 we
can run the perf tests that depend on sampling the timestamp.

On g4x/ilk we must read the udw of the 64bit timestamp
register. Details in {g4x,gen5)_read_clock_frequency().

When executing the read via the CS i965 doesn't seem to need
the double read trick that CPU mmio reads need.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031135703.14670-7-ville.syrjala@linux.intel.com
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index b11152f..881b64f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -39,6 +39,16 @@ static int perf_end(struct intel_gt *gt)
        return igt_flush_test(gt->i915);
 }
 
+static i915_reg_t timestamp_reg(struct intel_engine_cs *engine)
+{
+       struct drm_i915_private *i915 = engine->i915;
+
+       if (GRAPHICS_VER(i915) == 5 || IS_G4X(i915))
+               return RING_TIMESTAMP_UDW(engine->mmio_base);
+       else
+               return RING_TIMESTAMP(engine->mmio_base);
+}
+
 static int write_timestamp(struct i915_request *rq, int slot)
 {
        struct intel_timeline *tl =
@@ -55,7 +65,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
        if (GRAPHICS_VER(rq->engine->i915) >= 8)
                cmd++;
        *cs++ = cmd;
-       *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
+       *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
        *cs++ = tl->hwsp_offset + slot * sizeof(u32);
        *cs++ = 0;
 
@@ -125,7 +135,7 @@ static int perf_mi_bb_start(void *arg)
        enum intel_engine_id id;
        int err = 0;
 
-       if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */
+       if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
                return 0;
 
        perf_begin(gt);
@@ -252,7 +262,7 @@ static int perf_mi_noop(void *arg)
        enum intel_engine_id id;
        int err = 0;
 
-       if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */
+       if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
                return 0;
 
        perf_begin(gt);