[ValueTracking] Add more tests for `isKnownNonZero(Shift)`; NFC

Differential Revision: https://reviews.llvm.org/D148403

diff --git a/llvm/test/Analysis/ValueTracking/known-non-zero.ll b/llvm/test/Analysis/ValueTracking/known-non-zero.ll
index f6a0440..3468795 100644 (file)
--- a/llvm/test/Analysis/ValueTracking/known-non-zero.ll
+++ b/llvm/test/Analysis/ValueTracking/known-non-zero.ll
@@ -256,3 +256,201 @@ define i1 @shl_out_of_range_is_poison(i32 %v, i32 %c) {
   %z = icmp eq i32 %shl, 0
   ret i1 %z
 }
+
+define i1 @lshr_nz_bounded_cnt(i32 %cnt, i32 %y) {
+; CHECK-LABEL: @lshr_nz_bounded_cnt(
+; CHECK-NEXT:    [[CNT_ULT4:%.*]] = icmp ult i32 [[CNT:%.*]], 4
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CNT_ULT4]])
+; CHECK-NEXT:    [[VAL:%.*]] = or i32 [[Y:%.*]], 90
+; CHECK-NEXT:    [[SHL:%.*]] = lshr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt_ult4 = icmp ult i32 %cnt, 4
+  call void @llvm.assume(i1 %cnt_ult4)
+  %val = or i32 %y, 90
+  %shl = lshr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+define <2 x i1> @ashr_nz_bounded_cnt_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_nz_bounded_cnt_vec(
+; CHECK-NEXT:    [[CNT:%.*]] = and <2 x i32> [[X:%.*]], <i32 16, i32 24>
+; CHECK-NEXT:    [[VAL:%.*]] = or <2 x i32> [[Y:%.*]], <i32 402784272, i32 268697601>
+; CHECK-NEXT:    [[SHL:%.*]] = ashr <2 x i32> [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <2 x i32> [[SHL]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %cnt = and <2 x i32> %x, <i32 16, i32 24>
+  %val = or <2 x i32> %y, <i32 402784272, i32 268697601>
+  %shl = ashr <2 x i32> %val, %cnt
+  %r = icmp eq <2 x i32> %shl, zeroinitializer
+  ret <2 x i1> %r
+}
+
+
+define i1 @lshr_nz_bounded_cnt_fail(i32 %cnt, i32 %y) {
+; CHECK-LABEL: @lshr_nz_bounded_cnt_fail(
+; CHECK-NEXT:    [[CNT_ULT:%.*]] = icmp ult i32 [[CNT:%.*]], 20
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CNT_ULT]])
+; CHECK-NEXT:    [[VAL:%.*]] = or i32 [[Y:%.*]], 131072
+; CHECK-NEXT:    [[SHL:%.*]] = lshr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt_ult = icmp ult i32 %cnt, 20
+  call void @llvm.assume(i1 %cnt_ult)
+  %val = or i32 %y, 131072
+  %shl = lshr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+define <2 x i1> @ashr_nz_bounded_cnt_vec_fail(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_nz_bounded_cnt_vec_fail(
+; CHECK-NEXT:    [[CNT:%.*]] = and <2 x i32> [[X:%.*]], <i32 24, i32 24>
+; CHECK-NEXT:    [[VAL:%.*]] = or <2 x i32> [[Y:%.*]], <i32 131088, i32 268697601>
+; CHECK-NEXT:    [[SHL:%.*]] = ashr <2 x i32> [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <2 x i32> [[SHL]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %cnt = and <2 x i32> %x, <i32 24, i32 24>
+  %val = or <2 x i32> %y, <i32 131088, i32 268697601>
+  %shl = ashr <2 x i32> %val, %cnt
+  %r = icmp eq <2 x i32> %shl, zeroinitializer
+  ret <2 x i1> %r
+}
+
+
+
+
+define i1 @lshr_nonzero_and_shift_out_zeros(i32 %cnt, i32 %y) {
+; CHECK-LABEL: @lshr_nonzero_and_shift_out_zeros(
+; CHECK-NEXT:    [[CNT_ULT:%.*]] = icmp ult i32 [[CNT:%.*]], 4
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CNT_ULT]])
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], -131072
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = lshr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt_ult = icmp ult i32 %cnt, 4
+  call void @llvm.assume(i1 %cnt_ult)
+
+  %val = and i32 %y, -131072
+
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+
+  %shl = lshr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+
+define i1 @ashr_nonzero_and_shift_out_zeros(i32 %ccnt, i32 %y) {
+; CHECK-LABEL: @ashr_nonzero_and_shift_out_zeros(
+; CHECK-NEXT:    [[CNT:%.*]] = and i32 [[CCNT:%.*]], 7
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], -131072
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = ashr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt = and i32 %ccnt, 7
+  %val = and i32 %y, -131072
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+  %shl = ashr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+
+define i1 @shl_nonzero_and_shift_out_zeros(i32 %ccnt, i32 %y) {
+; CHECK-LABEL: @shl_nonzero_and_shift_out_zeros(
+; CHECK-NEXT:    [[CNT:%.*]] = and i32 [[CCNT:%.*]], 6
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], 131071
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt = and i32 %ccnt, 6
+  %val = and i32 %y, 131071
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+  %shl = shl i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+
+
+define i1 @lshr_nonzero_and_shift_out_zeros_fail(i32 %cnt, i32 %y) {
+; CHECK-LABEL: @lshr_nonzero_and_shift_out_zeros_fail(
+; CHECK-NEXT:    [[CNT_ULT:%.*]] = icmp ult i32 [[CNT:%.*]], 19
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CNT_ULT]])
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], -131072
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = lshr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt_ult = icmp ult i32 %cnt, 19
+  call void @llvm.assume(i1 %cnt_ult)
+
+  %val = and i32 %y, -131072
+
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+
+  %shl = lshr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+
+define i1 @ashr_nonzero_and_shift_out_zeros_fail(i32 %ccnt, i32 %y) {
+; CHECK-LABEL: @ashr_nonzero_and_shift_out_zeros_fail(
+; CHECK-NEXT:    [[CNT:%.*]] = and i32 [[CCNT:%.*]], 18
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], -131072
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = ashr i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt = and i32 %ccnt, 18
+  %val = and i32 %y, -131072
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+  %shl = ashr i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}
+
+
+define i1 @shl_nonzero_and_shift_out_zeros_fail(i32 %ccnt, i32 %y) {
+; CHECK-LABEL: @shl_nonzero_and_shift_out_zeros_fail(
+; CHECK-NEXT:    [[CNT:%.*]] = and i32 [[CCNT:%.*]], 6
+; CHECK-NEXT:    [[VAL:%.*]] = and i32 [[Y:%.*]], 268435455
+; CHECK-NEXT:    [[VAL_NZ:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[VAL_NZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[VAL]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cnt = and i32 %ccnt, 6
+  %val = and i32 %y, 268435455
+  %val_nz =  icmp ne i32 %val, 0
+  call void @llvm.assume(i1 %val_nz)
+  %shl = shl i32 %val, %cnt
+  %r = icmp eq i32 %shl, 0
+  ret i1 %r
+}