Create a version of this function that takes a CS and queue family.
move it to radv_cs.h so it can be called from multiple other files.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25770>
}
static void
-radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, unsigned engine_sel, uint64_t va, unsigned count,
- const uint32_t *data)
+radv_write_data(struct radv_cmd_buffer *cmd_buffer, const unsigned engine_sel, const uint64_t va, const unsigned count,
+ const uint32_t *data, const bool predicating)
{
- struct radeon_cmdbuf *cs = cmd_buffer->cs;
-
- radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
-
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
- radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- radeon_emit_array(cs, data, count);
+ radv_cs_write_data(cmd_buffer->device, cmd_buffer->cs, cmd_buffer->qf, engine_sel, va, count, data, predicating);
}
static void
{
uint32_t *zeroes = alloca(size);
memset(zeroes, 0, size);
- radv_emit_write_data_packet(cmd_buffer, engine_sel, va, size / 4, zeroes);
+ radv_write_data(cmd_buffer, engine_sel, va, size / 4, zeroes, false);
}
static void
va += 4;
++cmd_buffer->state.trace_id;
- radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 1, &cmd_buffer->state.trace_id);
+ radv_write_data(cmd_buffer, V_370_ME, va, 1, &cmd_buffer->state.trace_id, false);
radeon_check_space(cmd_buffer->device->ws, cs, 2);
data[0] = pipeline_address;
data[1] = pipeline_address >> 32;
- radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);
+ radv_write_data(cmd_buffer, V_370_ME, va, 2, data, false);
}
static void
data[0] = vb_ptr;
data[1] = vb_ptr >> 32;
- radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);
+ radv_write_data(cmd_buffer, V_370_ME, va, 2, data, false);
}
static void
data[0] = prolog_address;
data[1] = prolog_address >> 32;
- radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);
+ radv_write_data(cmd_buffer, V_370_ME, va, 2, data, false);
}
void
data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
}
- radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, MAX_SETS * 2, data);
+ radv_write_data(cmd_buffer, V_370_ME, va, MAX_SETS * 2, data, false);
}
const struct radv_userdata_info *
radeon_emit(cs, 4); /* poll interval */
}
+ALWAYS_INLINE static unsigned
+radv_cs_write_data_head(const struct radv_device *device, struct radeon_cmdbuf *cs, const enum radv_queue_family qf,
+ const unsigned engine_sel, const uint64_t va, const unsigned count, const bool predicating)
+{
+ assert(qf == RADV_QUEUE_GENERAL || qf == RADV_QUEUE_COMPUTE);
+
+ /* Return the correct cdw at the end of the packet so the caller can assert it. */
+ const unsigned cdw_end = radeon_check_space(device->ws, cs, 4 + count);
+
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, false));
+ radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+
+ return cdw_end;
+}
+
+ALWAYS_INLINE static void
+radv_cs_write_data(const struct radv_device *device, struct radeon_cmdbuf *cs, const enum radv_queue_family qf,
+ const unsigned engine_sel, const uint64_t va, const unsigned count, const uint32_t *dwords,
+ const bool predicating)
+{
+ ASSERTED const unsigned cdw_end = radv_cs_write_data_head(device, cs, qf, engine_sel, va, count, predicating);
+ radeon_emit_array(cs, dwords, count);
+ assert(cs->cdw == cdw_end);
+}
+
#endif /* RADV_CS_H */
void radv_device_init_msaa(struct radv_device *device);
VkResult radv_device_init_vrs_state(struct radv_device *device);
-void radv_emit_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm);
+void radv_cs_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm);
void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview,
VkClearDepthStencilValue ds_clear_value, VkImageAspectFlags aspects);
if (cmd_buffer->device->physical_device->use_ngg_streamout) {
/* generated prim counter */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va);
- radv_emit_write_data_imm(cs, V_370_ME, va + 4, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 4, 0x80000000);
/* written prim counter */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_XFB_OFFSET(index), va + 8);
- radv_emit_write_data_imm(cs, V_370_ME, va + 12, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 12, 0x80000000);
/* Record that the command buffer needs GDS. */
cmd_buffer->gds_needed = true;
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
/* On GFX11+, primitives generated query always use GDS. */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va);
- radv_emit_write_data_imm(cs, V_370_ME, va + 4, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 4, 0x80000000);
/* Record that the command buffer needs GDS. */
cmd_buffer->gds_needed = true;
if (cmd_buffer->device->physical_device->use_ngg_streamout) {
/* generated prim counter */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va + 16);
- radv_emit_write_data_imm(cs, V_370_ME, va + 20, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 20, 0x80000000);
/* written prim counter */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_XFB_OFFSET(index), va + 24);
- radv_emit_write_data_imm(cs, V_370_ME, va + 28, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 28, 0x80000000);
cmd_buffer->state.active_prims_xfb_gds_queries--;
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
/* On GFX11+, primitives generated query always use GDS. */
gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va + 16);
- radv_emit_write_data_imm(cs, V_370_ME, va + 20, 0x80000000);
+ radv_cs_write_data_imm(cs, V_370_ME, va + 20, 0x80000000);
cmd_buffer->state.active_prims_gen_gds_queries--;
}
void
-radv_emit_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm)
+radv_cs_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm)
{
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));