2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
inline function.
(_mm_mwait): Likewise.
* config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with
"mwait".
(sse3_monitor): Make it 32bit only.
(sse3_monitor64): New. 64bit monitor.
gcc/testsuite/
2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* gcc.target/i386/monitor.c: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@113617
138bc75d-0d04-0410-961f-
82ee72b054a4
+2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/24879
+ * config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
+ inline function.
+ (_mm_mwait): Likewise.
+
+ * config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with
+ "mwait".
+ (sse3_monitor): Make it 32bit only.
+ (sse3_monitor64): New. 64bit monitor.
+
2006-05-07 Volker Reichelt <reichelt@igpm.rwth-aachen.de>
PR target/27421
-/* Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
+/* Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
This file is part of GCC.
Public License. */
/* Implemented from the specification included in the Intel C++ Compiler
- User Guide and Reference, version 8.0. */
+ User Guide and Reference, version 9.0. */
#ifndef _PMMINTRIN_H_INCLUDED
#define _PMMINTRIN_H_INCLUDED
return (__m128i) __builtin_ia32_lddqu ((char const *)__P);
}
-#if 0
static __inline void __attribute__((__always_inline__))
_mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
{
{
__builtin_ia32_mwait (__E, __H);
}
-#else
-#define _mm_monitor(P, E, H) __builtin_ia32_monitor ((P), (E), (H))
-#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H))
-#endif
#endif /* __SSE3__ */
(match_operand:SI 1 "register_operand" "c")]
UNSPECV_MWAIT)]
"TARGET_SSE3"
- "mwait\t%0, %1"
+;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.
+;; Since 32bit register operands are implicitly zero extended to 64bit,
+;; we only need to set up 32bit registers.
+ "mwait"
[(set_attr "length" "3")])
(define_insn "sse3_monitor"
(match_operand:SI 1 "register_operand" "c")
(match_operand:SI 2 "register_operand" "d")]
UNSPECV_MONITOR)]
- "TARGET_SSE3"
+ "TARGET_SSE3 && !TARGET_64BIT"
"monitor\t%0, %1, %2"
[(set_attr "length" "3")])
+
+(define_insn "sse3_monitor64"
+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
+ (match_operand:SI 1 "register_operand" "c")
+ (match_operand:SI 2 "register_operand" "d")]
+ UNSPECV_MONITOR)]
+ "TARGET_SSE3 && TARGET_64BIT"
+;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
+;; RCX and RDX are used. Since 32bit register operands are implicitly
+;; zero extended to 64bit, we only need to set up 32bit registers.
+ "monitor"
+ [(set_attr "length" "3")])
+2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/24879
+ * gcc.target/i386/monitor.c: New file.
+
2006-05-08 Alan Modra <amodra@bigpond.net.au>
* gcc.dg/pr27095.c: xfail *-*-darwin*.
--- /dev/null
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -msse3" } */
+
+/* Verify that they work in both 32bit and 64bit. */
+
+#include <pmmintrin.h>
+
+void
+foo (char *p, int x, int y, int z)
+{
+ _mm_monitor (p, y, x);
+ _mm_mwait (z, y);
+}
+
+void
+bar (char *p, long x, long y, long z)
+{
+ _mm_monitor (p, y, x);
+ _mm_mwait (z, y);
+}
+
+void
+foo1 (char *p)
+{
+ _mm_monitor (p, 0, 0);
+ _mm_mwait (0, 0);
+}