net:fec: Disable enet-avb MAC instead of reset MAC

For i.MX6SX enet use AXI bus, reset MAC will make system bus dead
if ENET-AXI bus has pending access (AHB bus should not have such issue).
So, disable enet with AVB MAC instead of reset MAC itself.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 03972f7..5f8e997 100644 (file)
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -945,9 +945,16 @@ fec_restart(struct net_device *ndev)
        u32 rcntl = OPT_FRAME_SIZE | 0x04;
        u32 ecntl = 0x2; /* ETHEREN */
 
-       /* Whack a reset.  We should wait for this. */
-       writel(1, fep->hwp + FEC_ECNTRL);
-       udelay(10);
+       /* Whack a reset.  We should wait for this.
+        * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
+        * instead of reset MAC itself.
+        */
+       if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
+               writel(0, fep->hwp + FEC_ECNTRL);
+       } else {
+               writel(1, fep->hwp + FEC_ECNTRL);
+               udelay(10);
+       }
 
        /*
         * enet-mac reset will reset mac address registers too,
@@ -1118,9 +1125,16 @@ fec_stop(struct net_device *ndev)
                        netdev_err(ndev, "Graceful transmit stop did not complete!\n");
        }
 
-       /* Whack a reset.  We should wait for this. */
-       writel(1, fep->hwp + FEC_ECNTRL);
-       udelay(10);
+       /* Whack a reset.  We should wait for this.
+        * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
+        * instead of reset MAC itself.
+        */
+       if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
+               writel(0, fep->hwp + FEC_ECNTRL);
+       } else {
+               writel(1, fep->hwp + FEC_ECNTRL);
+               udelay(10);
+       }
        writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
        writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);