x86/msr: Lift AMD family 0x15 power-specific MSRs
authorBorislav Petkov <bp@suse.de>
Mon, 8 Jun 2020 14:19:49 +0000 (16:19 +0200)
committerBorislav Petkov <bp@suse.de>
Mon, 15 Jun 2020 17:25:53 +0000 (19:25 +0200)
... into the global msr-index.h header because they're used in multiple
compilation units. Sort the MSR list a bit. Update the msr-index.h copy
in tools.

No functional changes.

Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lkml.kernel.org/r/20200608164847.14232-1-bp@alien8.de
arch/x86/events/amd/power.c
arch/x86/include/asm/msr-index.h
drivers/hwmon/fam15h_power.c
tools/arch/x86/include/asm/msr-index.h

index 43b09e9c93a275a58e433f604b90114cdcea09a6..16a2369c586e88ed382477c09d60a72c98ab4263 100644 (file)
 #include <asm/cpu_device_id.h>
 #include "../perf_event.h"
 
-#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
-#define MSR_F15H_PTSC                  0xc0010280
-
 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
 #define AMD_POWER_EVENT_MASK           0xFFULL
 
index e8370e64a155cf27321d6727011d2e5883e4483f..eb9537254920cbceda66ac9f71a0b43e9646d1a7 100644 (file)
 #define MSR_AMD64_PATCH_LEVEL          0x0000008b
 #define MSR_AMD64_TSC_RATIO            0xc0000104
 #define MSR_AMD64_NB_CFG               0xc001001f
-#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_PATCH_LOADER         0xc0010020
 #define MSR_AMD_PERF_CTL               0xc0010062
 #define MSR_AMD_PERF_STATUS            0xc0010063
 #define MSR_AMD_PSTATE_DEF_BASE                0xc0010064
+#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
 #define MSR_AMD64_OSVW_ID_LENGTH       0xc0010140
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
+#define MSR_F15H_PTSC                  0xc0010280
 #define MSR_AMD_PPIN_CTL               0xc00102f0
 #define MSR_AMD_PPIN                   0xc00102f1
+#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_BU_CFG2              0xc001102a
index 267eac00a3fb330e91ee741f05606a3bab195002..29f5fed28c2a78c55d1bcd456ecf561f4fe94882 100644 (file)
@@ -41,10 +41,6 @@ MODULE_LICENSE("GPL");
 /* set maximum interval as 1 second */
 #define MAX_INTERVAL                   1000
 
-#define MSR_F15H_CU_PWR_ACCUMULATOR    0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR        0xc001007b
-#define MSR_F15H_PTSC                  0xc0010280
-
 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
 
 struct fam15h_power_data {
index ef452b817f44f31fa979ce25701a86f94c5e2a77..7dfd45bb6cdb321f4f3866e9589ca389013b5696 100644 (file)
 #define MSR_AMD64_PATCH_LEVEL          0x0000008b
 #define MSR_AMD64_TSC_RATIO            0xc0000104
 #define MSR_AMD64_NB_CFG               0xc001001f
-#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_PATCH_LOADER         0xc0010020
 #define MSR_AMD_PERF_CTL               0xc0010062
 #define MSR_AMD_PERF_STATUS            0xc0010063
 #define MSR_AMD_PSTATE_DEF_BASE                0xc0010064
+#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
 #define MSR_AMD64_OSVW_ID_LENGTH       0xc0010140
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
+#define MSR_F15H_PTSC                  0xc0010280
 #define MSR_AMD_PPIN_CTL               0xc00102f0
 #define MSR_AMD_PPIN                   0xc00102f1
+#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_BU_CFG2              0xc001102a