ARM: don't try to create an i8 -> i32 vpaddl.

DAG combine was mistakenly assuming that the step-up it was looking at was
always a doubling, but it can sometimes be a larger extension in which case
we'd crash.

llvm-svn: 301002

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0f8cdad..df840d7 100644 (file)
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -9480,8 +9480,11 @@ AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
       return SDValue();
   }
 
-  // Don't generate vpaddl+vmovn; we'll match it to vpadd later.
-  if (Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
+  // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also don't try
+  // to handle an i8 -> i32 situation (or similar). vpaddl can only double the
+  // size.
+  if (2 * Vec.getValueType().getVectorElementType().getSizeInBits() !=
+      VT.getVectorElementType().getSizeInBits())
     return SDValue();
 
   // Create VPADDL node.

diff --git a/llvm/test/CodeGen/ARM/vpadd.ll b/llvm/test/CodeGen/ARM/vpadd.ll
index 1aa2359..9720f80 100644 (file)
--- a/llvm/test/CodeGen/ARM/vpadd.ll
+++ b/llvm/test/CodeGen/ARM/vpadd.ll
@@ -485,6 +485,17 @@ define <2 x i16> @fromExtendingExtractVectorElt_i16(<4 x i16> %in) {
   ret <2 x i16> %x
 }
 
+; And <2 x i8> to <2 x i32>
+define <2 x i8> @fromExtendingExtractVectorElt_2i8(<8 x i8> %in) {
+; CHECK-LABEL: fromExtendingExtractVectorElt_2i8:
+; CHECK:    vadd.i32
+  %tmp1 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> <i32 0, i32 2>
+  %tmp2 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> <i32 1, i32 3>
+  %x = add <2 x i8> %tmp2, %tmp1
+  ret <2 x i8> %x
+}
+
+
 declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
 declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
 declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone