&AArch64::FPRRegBank;
};
- if (any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
+ LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
+ // UNMERGE into scalars from a vector should always use FPR.
+ // Likewise if any of the uses are FP instructions.
+ if (SrcTy.isVector() ||
+ any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
[&](MachineInstr &MI) { return HasFPConstraints(MI); })) {
// Set the register bank of every operand to FPR.
for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+---
+name: unmerge
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; Ensure that the dest regs have FPR since we're unmerging from a vector
+ ; CHECK-LABEL: name: unmerge
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
+ ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK: $x0 = COPY [[UV]](s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...