osd: add mali-afbc decode error statistics
authorpengcheng chen <pengcheng.chen@amlogic.com>
Mon, 11 Jun 2018 05:50:30 +0000 (13:50 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 29 Jun 2018 07:40:52 +0000 (00:40 -0700)
PD#165090: osd: add mali-afbc decode error statistics

Change-Id: Idb3c37944d3a0ac48422ab901416279fc458b00b
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
drivers/amlogic/media/osd/osd.h
drivers/amlogic/media/osd/osd_debug.c
drivers/amlogic/media/osd/osd_fb.c
drivers/amlogic/media/osd/osd_hw.c
drivers/amlogic/media/osd/osd_hw.h
drivers/amlogic/media/osd/osd_rdma.c

index 48844e9..21a1769 100644 (file)
@@ -719,6 +719,7 @@ struct hw_para_s {
        u32 hdr_used;
        u32 basic_urgent;
        u32 two_ports;
+       u32 afbc_err_cnt;
        struct hw_debug_s osd_debug;
        int out_fence_fd;
        int in_fd[HW_OSD_COUNT];
index d52da8a..9666960 100644 (file)
@@ -341,7 +341,8 @@ static void osd_debug_dump_register_all(void)
        }
 
        if (osd_hw.osd_meson_dev.cpu_id >= __MESON_CPU_MAJOR_ID_G12B) {
-               if (osd_hw.osd_meson_dev.has_viu2) {
+               if (osd_hw.osd_meson_dev.has_viu2 &&
+                       osd_hw.powered[OSD4]) {
                        reg = VPP2_MISC;
                        osd_log_info("reg[0x%x]: 0x%08x\n",
                                reg, osd_reg_read(reg));
index 744ecd5..35b7511 100644 (file)
@@ -2898,6 +2898,17 @@ static ssize_t store_osd_rotate(
        return count;
 }
 
+static ssize_t show_afbc_err_cnt(
+       struct device *device, struct device_attribute *attr,
+       char *buf)
+{
+       u32 err_cnt;
+
+       osd_get_afbc_err_cnt(&err_cnt);
+
+       return snprintf(buf, PAGE_SIZE, "%d\n", err_cnt);
+}
+
 static inline  int str2lower(char *str)
 {
        while (*str != '\0') {
@@ -3102,7 +3113,8 @@ static struct device_attribute osd_attrs[] = {
                        NULL, store_osd_single_step_mode),
        __ATTR(osd_single_step, 0220,
                        NULL, store_osd_single_step),
-
+       __ATTR(afbc_err_cnt, 0444,
+                       show_afbc_err_cnt, NULL),
 };
 
 static struct device_attribute osd_attrs_viu2[] = {
index 14eaa7a..fbb868a 100644 (file)
@@ -1401,8 +1401,10 @@ static bool mali_afbc_get_error(void)
        status = VSYNCOSD_RD_MPEG_REG(VPU_MAFBC_IRQ_RAW_STATUS);
        if (status & 0x3c) {
                osd_log_dbg("afbc error happened\n");
+               osd_hw.afbc_err_cnt++;
                error = true;
        }
+       status = VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_IRQ_CLEAR, 0x3f);
        return error;
 }
 static u32 osd_get_hw_reset_flag(void)
@@ -1449,9 +1451,8 @@ static u32 osd_get_hw_reset_flag(void)
                if (afbc_enable &&
                        osd_hw.afbc_force_reset)
                        hw_reset_flag |= HW_RESET_MALI_AFBCD_REGS;
-               if (afbc_enable &&
-                       osd_hw.afbc_status_err_reset &&
-                       mali_afbc_get_error())
+               if (afbc_enable && mali_afbc_get_error() &&
+                       osd_hw.afbc_status_err_reset)
                        hw_reset_flag |= HW_RESET_MALI_AFBCD_REGS;
                }
                break;
@@ -2938,6 +2939,11 @@ void osd_set_rotate(u32 index, u32 osd_rotate)
        osd_wait_vsync_hw();
 }
 
+void osd_get_afbc_err_cnt(u32 *err_cnt)
+{
+       *err_cnt = osd_hw.afbc_err_cnt;
+}
+
 int osd_get_capbility(u32 index)
 {
        u32 capbility = 0;
@@ -4442,10 +4448,15 @@ static void osd_update_disp_osd_reverse(u32 index)
        remove_from_update_list(index, DISP_OSD_REVERSE);
 }
 
+static int get_viu2_src_format(void)
+{
+       return RGBA;
+}
+
 static void osd_update_disp_osd_rotate(u32 index)
 {
        u32 rotate_en = osd_hw.osd_rotate[index];
-       u32 src_fmt = RGBA;
+       u32 src_fmt;
        u32 x_start, x_end, y_start, y_end;
        u32 src_width, src_height;
        u32 rot_hsize, blk_vsize, rd_blk_hsize;
@@ -4459,6 +4470,7 @@ static void osd_update_disp_osd_rotate(u32 index)
 
        if (osd_hw.osd_meson_dev.cpu_id < __MESON_CPU_MAJOR_ID_G12B)
                return;
+       src_fmt = get_viu2_src_format();
        src_data.x = 0;
        src_data.y = 0;
        src_data.w = osd_hw.fb_gem[index].xres;
@@ -7331,6 +7343,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
        osd_hw.osd_deband_enable = 1;
        osd_hw.out_fence_fd = -1;
        osd_hw.blend_bypass = 0;
+       osd_hw.afbc_err_cnt = 0;
        if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE) {
                data32 = osd_reg_read(
                        hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat);
index a0fcfba..8999cde 100644 (file)
@@ -200,4 +200,5 @@ void osd_set_single_step(u32 osd_single_step);
 void output_save_info(void);
 void osd_get_rotate(u32 index, u32 *osd_rotate);
 void osd_set_rotate(u32 index, u32 osd_rotate);
+void osd_get_afbc_err_cnt(u32 *err_cnt);
 #endif
index ae1d36b..03cab43 100644 (file)
@@ -342,7 +342,7 @@ static inline u32 is_rdma_reg(u32 addr)
 {
        u32 rdma_en = 1;
 
-       if ((addr >= 0x1e10) && (addr <= 0x1e50))
+       if ((addr >= VIU2_OSD1_CTRL_STAT) && (addr <= VIU2_OSD1_BLK3_CFG_W4))
                rdma_en = 0;
        else
                rdma_en = 1;