Add support for the new instructions in Prescott

diff --git a/disasm.c b/disasm.c
index 6daab42..dd63568 100644 (file)
--- a/disasm.c
+++ b/disasm.c
@@ -43,8 +43,12 @@ static int whichreg(long regflags, int regval)
        return R_AX;
     if (!(REG_EAX & ~regflags))
        return R_EAX;
+    if (!(REG_DL & ~regflags))
+       return R_DL;
     if (!(REG_DX & ~regflags))
        return R_DX;
+    if (!(REG_EDX & ~regflags))
+       return R_EDX;
     if (!(REG_CL & ~regflags))
        return R_CL;
     if (!(REG_CX & ~regflags))

diff --git a/insns.dat b/insns.dat
index 85ecc8e..d153786 100644 (file)
--- a/insns.dat
+++ b/insns.dat
@@ -318,6 +318,9 @@ FIST      mem16               \300\1\xDF\202                8086,FPU
 FISTP     mem32               \300\1\xDB\203                8086,FPU
 FISTP     mem16               \300\1\xDF\203                8086,FPU
 FISTP     mem64               \300\1\xDF\207                8086,FPU
+FISTTP    mem32               \300\1\xDD\201                PRESCOTT,FPU
+FISTTP    mem16               \300\1\xDB\201                PRESCOTT,FPU
+FISTTP    mem64               \300\1\xDF\201                PRESCOTT,FPU
 FISUB     mem32               \300\1\xDA\204                8086,FPU
 FISUB     mem16               \300\1\xDE\204                8086,FPU
 FISUBR    mem32               \300\1\xDA\205                8086,FPU
@@ -563,6 +566,8 @@ LSS       reg32,mem           \321\301\2\x0F\xB2\110        386
 LTR       mem                 \300\1\x0F\17\203             286,PROT,PRIV
 LTR       mem16               \300\1\x0F\17\203             286,PROT,PRIV
 LTR       reg16               \1\x0F\17\203                 286,PROT,PRIV
+MONITOR   void               \3\x0F\x01\xC8                PRESCOTT
+MONITOR          reg_eax,reg_ecx,reg_edx      \3\x0F\x01\xC8       PRESCOTT,ND
 MOV       mem,reg_sreg        \300\1\x8C\101                8086,SM
 MOV       reg16,reg_sreg      \320\1\x8C\101                8086
 MOV       reg32,reg_sreg      \321\1\x8C\101                386
@@ -624,6 +629,8 @@ MOVZX     reg32,rm16          \321\301\2\x0F\xB7\110        386
 MUL       rm8                 \300\1\xF6\204                8086
 MUL       rm16                \320\300\1\xF7\204            8086
 MUL       rm32                \321\300\1\xF7\204            386
+MWAIT    void                \3\x0F\x01\xC9                PRESCOTT
+MWAIT    reg_eax,reg_ecx     \3\x0F\x01\xC9                PRESCOTT,ND
 NEG       rm8                 \300\1\xF6\203                8086
 NEG       rm16                \320\300\1\xF7\203            8086
 NEG       rm32                \321\300\1\xF7\203            386
@@ -1641,3 +1648,24 @@ UNPCKLPD        xmmreg,xmmreg           \3\x66\x0F\x14\110              WILLAMET
 UNPCKLPD        xmmreg,mem              \301\3\x66\x0F\x14\110          WILLAMETTE,SSE2,SM
 XORPD           xmmreg,xmmreg           \3\x66\x0F\x57\110              WILLAMETTE,SSE2
 XORPD           xmmreg,mem              \301\3\x66\x0F\x57\110          WILLAMETTE,SSE2,SM
+
+; Prescott New Instructions (SSE3)
+ADDSUBPD        xmmreg,mem              \301\3\x66\x0F\xD0\110          PRESCOTT,SSE3,SM
+ADDSUBPD       xmmreg,xmmreg           \3\x66\x0F\xD0\110              PRESCOTT,SSE3
+ADDSUBPS       xmmreg,mem              \301\3\xF2\x0F\xD0\110          PRESCOTT,SSE3,SM
+ADDSUBPS       xmmreg,xmmreg           \3\xF2\x0F\xD0\110              PRESCOTT,SSE3
+HADDPD         xmmreg,mem              \301\3\x66\x0F\x7C\110          PRESCOTT,SSE3,SM
+HADDPD         xmmreg,xmmreg           \3\x66\x0F\x7C\110              PRESCOTT,SSE3
+HADDPS         xmmreg,mem              \301\3\xF2\x0F\x7C\110          PRESCOTT,SSE3,SM
+HADDPS         xmmreg,xmmreg           \3\xF2\x0F\x7C\110              PRESCOTT,SSE3
+HSUBPD         xmmreg,mem              \301\3\x66\x0F\x7D\110          PRESCOTT,SSE3,SM
+HSUBPD         xmmreg,xmmreg           \3\x66\x0F\x7D\110              PRESCOTT,SSE3
+HSUBPS         xmmreg,mem              \301\3\xF2\x0F\x7D\110          PRESCOTT,SSE3,SM
+HSUBPS         xmmreg,xmmreg           \3\xF2\x0F\x7D\110              PRESCOTT,SSE3
+LDDQU          xmmreg,mem              \3\xF2\x0F\xF0\110              PRESCOTT,SSE3
+MOVDDUP                xmmreg,mem              \301\3\xF2\x0F\x12\110          PRESCOTT,SSE3
+MOVDDUP                xmmreg,xmmreg           \3\xF2\x0F\x12\110              PRESCOTT,SSE3
+MOVSHDUP       xmmreg,mem              \301\3\xF3\x0F\x16\110          PRESCOTT,SSE3
+MOVSHDUP       xmmreg,xmmreg           \3\xF3\x0F\x16\110              PRESCOTT,SSE3
+MOVSLDUP       xmmreg,mem              \301\3\xF3\x0F\x12\110          PRESCOTT,SSE3
+MOVSLDUP       xmmreg,xmmreg           \3\xF3\x0F\x12\110              PRESCOTT,SSE3

diff --git a/insns.h b/insns.h
index 3fb2d84..e2f1145 100644 (file)
--- a/insns.h
+++ b/insns.h
@@ -77,6 +77,7 @@ struct itemplate {
 #define IF_3DNOW  0x00008000UL        /* it's a 3DNow! instruction */
 #define IF_SSE    0x00010000UL        /* it's a SSE (KNI, MMX2) instruction */
 #define IF_SSE2   0x00020000UL        /* it's a SSE2 instruction */
+#define IF_SSE3   0x00040000UL        /* it's a SSE3 (PNI) instruction */
 #define IF_PMASK  0xFF000000UL        /* the mask for processor types */
 #define IF_PLEVEL 0x0F000000UL         /* the mask for processor instr. level */
                                        /* also the highest possible processor */
@@ -90,6 +91,7 @@ struct itemplate {
 #define IF_P6     0x06000000UL        /* P6 instruction */
 #define IF_KATMAI 0x07000000UL         /* Katmai instructions */
 #define IF_WILLAMETTE 0x08000000UL         /* Willamette instructions */
+#define IF_PRESCOTT   0x09000000UL     /* Prescott instructions */
 #define IF_IA64   0x0F000000UL        /* IA64 instructions */
 #define IF_CYRIX  0x10000000UL        /* Cyrix-specific instruction */
 #define IF_AMD    0x20000000UL        /* AMD-specific instruction */

diff --git a/nasm.c b/nasm.c
index 5d37a34..b63c8f6 100644 (file)
--- a/nasm.c
+++ b/nasm.c
@@ -1635,6 +1635,7 @@ static unsigned long get_cpu (char *value)
        !nasm_stricmp(value, "katmai") )        return IF_KATMAI;
     if (!nasm_stricmp(value, "p4")    ||       /* is this right? -- jrc */
        !nasm_stricmp(value, "willamette") )    return IF_WILLAMETTE;
+    if (!nasm_stricmp(value, "prescott") )      return IF_PRESCOTT;
     if (!nasm_stricmp(value, "ia64") ||
        !nasm_stricmp(value, "ia-64") ||
        !nasm_stricmp(value, "itanium") ||

diff --git a/nasm.h b/nasm.h
index 8f4f293..6ead7c2 100644 (file)
--- a/nasm.h
+++ b/nasm.h
@@ -410,7 +410,9 @@ enum {
 #define REG_CL    0x00221001L         /* REG_COUNT | BITSxx */
 #define REG_CX    0x00221002L         /* ditto */
 #define REG_ECX   0x00221004L         /* another one */
+#define REG_DL    0x00241001L
 #define REG_DX    0x00241002L
+#define REG_EDX   0x00241004L
 #define REG_SREG  0x00081002L         /* any segment register */
 #define REG_CS    0x01081002L         /* CS */
 #define REG_DESS  0x02081002L         /* DS, ES, SS (non-CS 86 registers) */

diff --git a/regs.dat b/regs.dat
index c294a7b..f2bb8e8 100644 (file)
--- a/regs.dat
+++ b/regs.dat
@@ -19,10 +19,10 @@ cl  REG_CL          reg8    1
 ch     REG8            reg8    5
 cx     REG_CX          reg16   1
 ecx    REG_ECX         reg32   1
-dl     REG8            reg8    2
+dl     REG_DL          reg8    2
 dh     REG8            reg8    6
 dx     REG_DX          reg16   2
-edx    REG32           reg32   2
+edx    REG_EDX         reg32   2
 sp     REG16           reg16   4
 esp    REG32           reg32   4
 bp     REG16           reg16   5