drm/i915: Wire up pipe CRC support for bdw

The layout of the CRC registers is the same as on hsw, only the
interrupt handling has changed a bit. So trivial to wire up, yay!

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4420944..a06de99 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1808,6 +1808,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
                        intel_finish_page_flip_plane(dev, pipe);
                }
 
+               if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
+                       hsw_pipe_crc_irq_handler(dev, pipe);
+
                if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
                        DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
                                  pipe_name(pipe),
@@ -2898,6 +2901,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        struct drm_device *dev = dev_priv->dev;
        uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
                                   GEN8_PIPE_VBLANK |
+                                  GEN8_PIPE_CDCLK_CRC_DONE |
                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
        int pipe;
        dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;