phy: mediatek: hdmi: mt8173: use common helper to access registers

Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-12-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 8f93991..d047583 100644 (file)
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -5,6 +5,7 @@
  */
 
 #include "phy-mtk-hdmi.h"
+#include "phy-mtk-io.h"
 
 #define HDMI_CON0              0x00
 #define RG_HDMITX_PLL_EN               BIT(31)
@@ -86,16 +87,17 @@
 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 {
        struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+       void __iomem *base = hdmi_phy->regs;
 
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+       mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+       mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+       mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN);
+       mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
        usleep_range(100, 150);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+       mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
        usleep_range(100, 150);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+       mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+       mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
 
        return 0;
 }
@@ -103,15 +105,16 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
 {
        struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+       void __iomem *base = hdmi_phy->regs;
 
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+       mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+       mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
        usleep_range(100, 150);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+       mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
        usleep_range(100, 150);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+       mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+       mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+       mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
        usleep_range(100, 150);
 }
 
@@ -133,6 +136,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long parent_rate)
 {
        struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+       void __iomem *base = hdmi_phy->regs;
        unsigned int pre_div;
        unsigned int div;
        unsigned int pre_ibias;
@@ -153,71 +157,57 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                div = 1;
        }
 
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-                         FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
-                         RG_HDMITX_PLL_PREDIV);
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-                         FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
-                         FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
-                         RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
-                         FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
-                         RG_HDMITX_PLL_TXDIV);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-                         FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
-                         FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
-                         RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
-                         FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
-                         RG_HDMITX_PLL_DIVEN);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
-                         FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
-                         FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
-                         FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
-                         RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
-                         RG_HDMITX_PLL_BR);
+       mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div);
+       mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+       mtk_phy_update_bits(base + HDMI_CON0,
+                           RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
+                           FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
+                           FIELD_PREP(RG_HDMITX_PLL_IR, 0x1));
+       mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div);
+       mtk_phy_update_bits(base + HDMI_CON0,
+                           RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
+                           FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
+                           FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19));
+       mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2);
+       mtk_phy_update_bits(base + HDMI_CON0,
+                           RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
+                           RG_HDMITX_PLL_BR,
+                           FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
+                           FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
+                           FIELD_PREP(RG_HDMITX_PLL_BR, 0x1));
        if (rate < 165000000) {
-               mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
-                                       RG_HDMITX_PRD_IMP_EN);
+               mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
                pre_ibias = 0x3;
                imp_en = 0x0;
                hdmi_ibias = hdmi_phy->ibias;
        } else {
-               mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
-                                     RG_HDMITX_PRD_IMP_EN);
+               mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
                pre_ibias = 0x6;
                imp_en = 0xf;
                hdmi_ibias = hdmi_phy->ibias_up;
        }
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
-                         FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
-                         FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
-                         FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
-                         FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
-                         RG_HDMITX_PRD_IBIAS_CLK |
-                         RG_HDMITX_PRD_IBIAS_D2 |
-                         RG_HDMITX_PRD_IBIAS_D1 |
-                         RG_HDMITX_PRD_IBIAS_D0);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
-                         FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
-                         RG_HDMITX_DRV_IMP_EN);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
-                         FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
-                         FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
-                         FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
-                         FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
-                         RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
-                         RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
-       mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
-                         FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
-                         FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
-                         FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
-                         FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
-                         RG_HDMITX_DRV_IBIAS_CLK |
-                         RG_HDMITX_DRV_IBIAS_D2 |
-                         RG_HDMITX_DRV_IBIAS_D1 |
-                         RG_HDMITX_DRV_IBIAS_D0);
+       mtk_phy_update_bits(base + HDMI_CON4,
+                           RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 |
+                           RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0,
+                           FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
+                           FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
+                           FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
+                           FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias));
+       mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en);
+       mtk_phy_update_bits(base + HDMI_CON6,
+                           RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
+                           RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
+                           FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
+                           FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
+                           FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
+                           FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0));
+       mtk_phy_update_bits(base + HDMI_CON5,
+                           RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
+                           RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0,
+                           FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
+                           FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
+                           FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
+                           FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias));
        return 0;
 }
 
@@ -239,17 +229,17 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
 
 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-       mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
-                             RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
-                             RG_HDMITX_DRV_EN);
+       mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3,
+                        RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
+                        RG_HDMITX_DRV_EN);
        usleep_range(100, 150);
 }
 
 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
 {
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
-                               RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
-                               RG_HDMITX_SER_EN);
+       mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3,
+                          RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
+                          RG_HDMITX_SER_EN);
 }
 
 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {