drm/i915: use gtt_get_size() instead of open coding it
authorImre Deak <imre.deak@intel.com>
Mon, 7 Jan 2013 19:47:35 +0000 (21:47 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 17 Jan 2013 21:07:56 +0000 (22:07 +0100)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_tiling.c

index 0b09361..35ecabc 100644 (file)
@@ -1565,6 +1565,8 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
 uint32_t
+i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
+uint32_t
 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
                            int tiling_mode, bool fenced);
 
index 718574e..313bdba 100644 (file)
@@ -1435,7 +1435,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
        obj->fault_mappable = false;
 }
 
-static uint32_t
+uint32_t
 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
 {
        uint32_t gtt_size;
index cb71ded..e76f0d8 100644 (file)
@@ -272,18 +272,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
                        return false;
        }
 
-       /*
-        * Previous chips need to be aligned to the size of the smallest
-        * fence register that can contain the object.
-        */
-       if (INTEL_INFO(obj->base.dev)->gen == 3)
-               size = 1024*1024;
-       else
-               size = 512*1024;
-
-       while (size < obj->base.size)
-               size <<= 1;
-
+       size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
        if (obj->gtt_space->size != size)
                return false;