ARM: dts: rockchip: Add Rockchip RV1126 pinctrl

Add pinctrl definitions for Rockchip RV1126.

From RK3568 on-wards pinctrl configurations are maintained
in common conf file rockchip-pinconf.dtsi and it is available
in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi).

So, include the same conf file to RV1126 pinctrl from arm64 path.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-4-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/MAINTAINERS b/MAINTAINERS
index f61eb22..a71b0af 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2807,7 +2807,7 @@ F:        Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
 F:     Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
 F:     Documentation/devicetree/bindings/spi/spi-rockchip.yaml
 F:     arch/arm/boot/dts/rk3*
-F:     arch/arm/boot/dts/rv1108*
+F:     arch/arm/boot/dts/rv11*
 F:     arch/arm/mach-rockchip/
 F:     drivers/*/*/*rockchip*
 F:     drivers/*/*rockchip*

diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..4bc419c
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+       emmc {
+               /omit-if-no-ref/
+               emmc_rstnout: emmc-rstnout {
+                       rockchip,pins =
+                               /* emmc_rstn */
+                               <1 RK_PA3 2 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               emmc_bus8: emmc-bus8 {
+                       rockchip,pins =
+                               /* emmc_d0 */
+                               <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d1 */
+                               <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d2 */
+                               <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d3 */
+                               <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d4 */
+                               <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d5 */
+                               <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d6 */
+                               <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+                               /* emmc_d7 */
+                               <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               emmc_clk: emmc-clk {
+                       rockchip,pins =
+                               /* emmc_clko */
+                               <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               emmc_cmd: emmc-cmd {
+                       rockchip,pins =
+                               /* emmc_cmd */
+                               <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+               };
+       };
+       i2c0 {
+               /omit-if-no-ref/
+               i2c0_xfer: i2c0-xfer {
+                       rockchip,pins =
+                               /* i2c0_scl */
+                               <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+                               /* i2c0_sda */
+                               <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+               };
+       };
+       sdmmc0 {
+               /omit-if-no-ref/
+               sdmmc0_bus4: sdmmc0-bus4 {
+                       rockchip,pins =
+                               /* sdmmc0_d0 */
+                               <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc0_d1 */
+                               <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc0_d2 */
+                               <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc0_d3 */
+                               <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc0_clk: sdmmc0-clk {
+                       rockchip,pins =
+                               /* sdmmc0_clk */
+                               <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc0_cmd: sdmmc0-cmd {
+                       rockchip,pins =
+                               /* sdmmc0_cmd */
+                               <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc0_det: sdmmc0-det {
+                       rockchip,pins =
+                               <0 RK_PA3 1 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               sdmmc0_pwr: sdmmc0-pwr {
+                       rockchip,pins =
+                               <0 RK_PC0 1 &pcfg_pull_none>;
+               };
+       };
+       sdmmc1 {
+               /omit-if-no-ref/
+               sdmmc1_bus4: sdmmc1-bus4 {
+                       rockchip,pins =
+                               /* sdmmc1_d0 */
+                               <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc1_d1 */
+                               <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc1_d2 */
+                               <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+                               /* sdmmc1_d3 */
+                               <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc1_clk: sdmmc1-clk {
+                       rockchip,pins =
+                               /* sdmmc1_clk */
+                               <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc1_cmd: sdmmc1-cmd {
+                       rockchip,pins =
+                               /* sdmmc1_cmd */
+                               <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+               };
+               /omit-if-no-ref/
+               sdmmc1_det: sdmmc1-det {
+                       rockchip,pins =
+                               <1 RK_PD0 2 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               sdmmc1_pwr: sdmmc1-pwr {
+                       rockchip,pins =
+                               <1 RK_PD1 2 &pcfg_pull_none>;
+               };
+       };
+       uart0 {
+               /omit-if-no-ref/
+               uart0_xfer: uart0-xfer {
+                       rockchip,pins =
+                               /* uart0_rx */
+                               <1 RK_PC2 1 &pcfg_pull_up>,
+                               /* uart0_tx */
+                               <1 RK_PC3 1 &pcfg_pull_up>;
+               };
+               /omit-if-no-ref/
+               uart0_ctsn: uart0-ctsn {
+                       rockchip,pins =
+                               <1 RK_PC1 1 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               uart0_rtsn: uart0-rtsn {
+                       rockchip,pins =
+                               <1 RK_PC0 1 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               uart0_rtsn_gpio: uart0-rts-pin {
+                       rockchip,pins =
+                               <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+       uart1 {
+               /omit-if-no-ref/
+               uart1m0_xfer: uart1m0-xfer {
+                       rockchip,pins =
+                               /* uart1_rx_m0 */
+                               <0 RK_PB7 2 &pcfg_pull_up>,
+                               /* uart1_tx_m0 */
+                               <0 RK_PB6 2 &pcfg_pull_up>;
+               };
+       };
+       uart2 {
+               /omit-if-no-ref/
+               uart2m1_xfer: uart2m1-xfer {
+                       rockchip,pins =
+                               /* uart2_rx_m1 */
+                               <3 RK_PA3 1 &pcfg_pull_up>,
+                               /* uart2_tx_m1 */
+                               <3 RK_PA2 1 &pcfg_pull_up>;
+               };
+       };
+       uart3 {
+               /omit-if-no-ref/
+               uart3m0_xfer: uart3m0-xfer {
+                       rockchip,pins =
+                               /* uart3_rx_m0 */
+                               <3 RK_PC7 4 &pcfg_pull_up>,
+                               /* uart3_tx_m0 */
+                               <3 RK_PC6 4 &pcfg_pull_up>;
+               };
+       };
+       uart4 {
+               /omit-if-no-ref/
+               uart4m0_xfer: uart4m0-xfer {
+                       rockchip,pins =
+                               /* uart4_rx_m0 */
+                               <3 RK_PA5 4 &pcfg_pull_up>,
+                               /* uart4_tx_m0 */
+                               <3 RK_PA4 4 &pcfg_pull_up>;
+               };
+       };
+       uart5 {
+               /omit-if-no-ref/
+               uart5m0_xfer: uart5m0-xfer {
+                       rockchip,pins =
+                               /* uart5_rx_m0 */
+                               <3 RK_PA7 4 &pcfg_pull_up>,
+                               /* uart5_tx_m0 */
+                               <3 RK_PA6 4 &pcfg_pull_up>;
+               };
+       };
+};