imx8ulp: clock: Support to enable/disable the ADC1 clock

This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index 745fd7f..e15ef1d 100644 (file)
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -56,6 +56,10 @@ enum cgc_clk {
        PLL4_PFD2_DIV2,
        PLL4_PFD3_DIV1,
        PLL4_PFD3_DIV2,
+       CM33_BUSCLK,
+       PLL1_VCO_DIV,
+       PLL0_PFD2_DIV,
+       PLL0_PFD1_DIV,
 };
 
 struct cgc1_regs {

diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index cc70284..c0f32cc 100644 (file)
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -41,4 +41,5 @@ void cgc1_enet_stamp_sel(u32 clk_src);
 void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
 void reset_lcdclk(void);
 void enable_mipi_dsi_clk(unsigned char enable);
+void enable_adc1_clk(bool enable);
 #endif

diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index af6845c..91adc85 100644 (file)
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -30,6 +30,7 @@
 
 #define PCC_XRDC_MGR_ADDR      0x292d00bc
 
+#define PCC1_RBASE             0x28091000
 #define PCC3_RBASE             0x292d0000
 #define PCC4_RBASE             0x29800000
 #define PCC5_RBASE             0x2da70000

diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 4680154..46386f1 100644 (file)
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -8,6 +8,10 @@
 
 #include <asm/arch/cgc.h>
 
+enum pcc1_entry {
+       ADC1_PCC1_SLOT = 34,
+};
+
 enum pcc3_entry {
        DMA1_MP_PCC3_SLOT = 1,
        DMA1_CH0_PCC3_SLOT = 2,

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index d03269a..9617023 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -341,6 +341,18 @@ void enable_mipi_dsi_clk(unsigned char enable)
        }
 }
 
+void enable_adc1_clk(bool enable)
+{
+       if (enable) {
+               pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
+               pcc_clock_sel(1, ADC1_PCC1_SLOT, CM33_BUSCLK);
+               pcc_clock_enable(1, ADC1_PCC1_SLOT, true);
+               pcc_reset_peripheral(1, ADC1_PCC1_SLOT, false);
+       } else {
+               pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
+       }
+}
+
 void reset_lcdclk(void)
 {
        /* Disable clock and reset dcnano*/

diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c
index 6145b3e..7909d77 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/pcc.c
+++ b/arch/arm/mach-imx/imx8ulp/pcc.c
@@ -15,6 +15,21 @@
 #define cgc_clk_TYPES 2
 #define cgc_clk_NUM 8
 
+static enum cgc_clk pcc1_clksrc[][8] = {
+       {
+       },
+       {
+               DUMMY0_CLK,
+               LPOSC,
+               SOSC_DIV2,
+               FRO_DIV2,
+               CM33_BUSCLK,
+               PLL1_VCO_DIV,
+               PLL0_PFD2_DIV,
+               PLL0_PFD1_DIV,
+       }
+};
+
 static enum cgc_clk pcc3_clksrc[][8] = {
        {
        },
@@ -75,6 +90,11 @@ static enum cgc_clk pcc5_clksrc[][8] = {
        }
 };
 
+static struct pcc_entry pcc1_arrays[] = {
+       {PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B},
+       {}
+};
+
 static struct pcc_entry pcc3_arrays[] = {
        {PCC3_RBASE, DMA1_MP_PCC3_SLOT,         CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
        {PCC3_RBASE, DMA1_CH0_PCC3_SLOT,        CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
@@ -228,6 +248,10 @@ static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry
        int index = 0;
 
        switch (pcc_controller) {
+       case 1:
+               pcc_array = pcc1_arrays;
+               *out = &pcc1_arrays[0];
+               break;
        case 3:
                pcc_array = pcc3_arrays;
                *out = &pcc3_arrays[0];
@@ -310,7 +334,9 @@ int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src)
                return -EPERM;
        }
 
-       if (pcc_controller == 3)
+       if (pcc_controller == 1)
+               cgc_clk_array = pcc1_clksrc[clksrc_type];
+       else if (pcc_controller == 3)
                cgc_clk_array = pcc3_clksrc[clksrc_type];
        else if (pcc_controller == 4)
                cgc_clk_array = pcc4_clksrc[clksrc_type];