{
uint32_t val;
- vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
+ if (phy == 0)
+ vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
+ else
+ vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val);
return val;
}
*/
void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
- vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
+ if (phy == 0)
+ vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
+ else
+ vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val);
}
uint32_t intel_flisdsi_reg_read(uint32_t reg)
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
+#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_GPIO_NC 0x13
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_CCU 0xA9