MIPS: Always use IRQ domains for CPU IRQs

Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7799/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f43aa53..92033b7 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1055,6 +1055,7 @@ config MIPS_HUGE_TLB_SUPPORT
 
 config IRQ_CPU
        bool
+       select IRQ_DOMAIN
 
 config IRQ_CPU_RM7K
        bool

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index e498f2b..b097f7d 100644 (file)
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -94,28 +94,6 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
        .irq_eoi        = unmask_mips_irq,
 };
 
-void __init mips_cpu_irq_init(void)
-{
-       int irq_base = MIPS_CPU_IRQ_BASE;
-       int i;
-
-       /* Mask interrupts. */
-       clear_c0_status(ST0_IM);
-       clear_c0_cause(CAUSEF_IP);
-
-       /* Software interrupts are used for MT/CMT IPI */
-       for (i = irq_base; i < irq_base + 2; i++)
-               irq_set_chip_and_handler(i, cpu_has_mipsmt ?
-                                        &mips_mt_cpu_irq_controller :
-                                        &mips_cpu_irq_controller,
-                                        handle_percpu_irq);
-
-       for (i = irq_base + 2; i < irq_base + 8; i++)
-               irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
-                                        handle_percpu_irq);
-}
-
-#ifdef CONFIG_IRQ_DOMAIN
 static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
                             irq_hw_number_t hw)
 {
@@ -138,8 +116,7 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
        .xlate = irq_domain_xlate_onecell,
 };
 
-int __init mips_cpu_intc_init(struct device_node *of_node,
-                             struct device_node *parent)
+static void __init __mips_cpu_irq_init(struct device_node *of_node)
 {
        struct irq_domain *domain;
 
@@ -151,7 +128,16 @@ int __init mips_cpu_intc_init(struct device_node *of_node,
                                       &mips_cpu_intc_irq_domain_ops, NULL);
        if (!domain)
                panic("Failed to add irqdomain for MIPS CPU");
+}
+
+void __init mips_cpu_irq_init(void)
+{
+       __mips_cpu_irq_init(NULL);
+}
 
+int __init mips_cpu_intc_init(struct device_node *of_node,
+                             struct device_node *parent)
+{
+       __mips_cpu_irq_init(of_node);
        return 0;
 }
-#endif /* CONFIG_IRQ_DOMAIN */