arm64: dts: qcom: sm6375: Hook up MPM

[ Upstream commit d3246a0cf43fd24a1986163284edd2389143809d ]

Add a node for MPM and wire it up on consumers that use it. This also
fixes a very bad and sad assumption I made when initially porting this
SoC that the downstream MPM-TLMM mappings were 1-1. That apparently
changed some time ago, so with this patch the MPM consumers will actually
be hooked up to the correct interrupt lines.

Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231215-topic-mpm_dt-v1-1-c6636fc75ce3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index b479f3d..e56f7ea 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -311,6 +311,25 @@
                };
        };
 
+       mpm: interrupt-controller {
+               compatible = "qcom,mpm";
+               qcom,rpm-msg-ram = <&apss_mpm>;
+               interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+               mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               #power-domain-cells = <0>;
+               interrupt-parent = <&intc>;
+               qcom,mpm-pin-count = <96>;
+               qcom,mpm-pin-map = <5 296>,  /* Soundwire wake_irq */
+                                  <12 422>, /* DWC3 ss_phy_irq */
+                                  <86 183>, /* MPM wake, SPMI */
+                                  <89 314>, /* TSENS0 0C */
+                                  <90 315>, /* TSENS1 0C */
+                                  <93 164>, /* DWC3 dm_hs_phy_irq */
+                                  <94 165>; /* DWC3 dp_hs_phy_irq */
+       };
+
        memory@80000000 {
                device_type = "memory";
                /* We expect the bootloader to fill in the size */
@@ -486,6 +505,7 @@
 
                CLUSTER_PD: power-domain-cpu-cluster0 {
                        #power-domain-cells = <0>;
+                       power-domains = <&mpm>;
                        domain-idle-states = <&CLUSTER_SLEEP_0>;
                };
        };
@@ -808,7 +828,7 @@
                        reg = <0 0x00500000 0 0x800000>;
                        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
                        gpio-ranges = <&tlmm 0 0 157>;
-                       /* TODO: Hook up MPM as wakeup-parent when it's there */
+                       wakeup-parent = <&mpm>;
                        interrupt-controller;
                        gpio-controller;
                        #interrupt-cells = <2>;
@@ -930,7 +950,7 @@
                              <0 0x01c0a000 0 0x26000>;
                        reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
                        interrupt-names = "periph_irq";
-                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
                        qcom,ee = <0>;
                        qcom,channel = <0>;
                        #address-cells = <2>;
@@ -962,8 +982,15 @@
                };
 
                rpm_msg_ram: sram@45f0000 {
-                       compatible = "qcom,rpm-msg-ram";
+                       compatible = "qcom,rpm-msg-ram", "mmio-sram";
                        reg = <0 0x045f0000 0 0x7000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x0 0x045f0000 0x7000>;
+
+                       apss_mpm: sram@1b8 {
+                               reg = <0x1b8 0x48>;
+                       };
                };
 
                sram@4690000 {
@@ -1360,10 +1387,10 @@
                                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <133333333>;
 
-                       interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 93 IRQ_TYPE_EDGE_BOTH>,
-                                    <GIC_SPI 94 IRQ_TYPE_EDGE_BOTH>;
+                       interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&mpm 12 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&mpm 93 IRQ_TYPE_EDGE_BOTH>,
+                                             <&mpm 94 IRQ_TYPE_EDGE_BOTH>;
                        interrupt-names = "hs_phy_irq",
                                          "ss_phy_irq",
                                          "dm_hs_phy_irq",