aarch64-simd.md (vec_extract): New.

2013-11-13  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (vec_extract): New.

From-SVN: r204747

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 331e61c..8f98926 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2013-11-13  Tejas Belagod  <tejas.belagod@arm.com>
 
+       * config/aarch64/aarch64-simd.md (vec_extract): New.
+
+2013-11-13  Tejas Belagod  <tejas.belagod@arm.com>
+
        * config/aarch64/aarch64-simd.md (vec_set<mode>): Add w -> w option to
        the constraint.
 

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index df4ef95..0b16b05 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4582,3 +4582,19 @@
    (set_attr "simd_mode" "<MODE>")]
 )
 
+;; Standard pattern name vec_extract<mode>.
+
+(define_insn "vec_extract<mode>"
+  [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv")
+       (vec_select:<VEL>
+         (match_operand:VALL 1 "register_operand" "w, w, w")
+         (parallel [(match_operand:SI 2 "immediate_operand" "i,i,i")])))]
+  "TARGET_SIMD"
+  "@
+  umov\\t%<vw>0, %1.<Vetype>[%2]
+  dup\\t%<Vetype>0, %1.<Vetype>[%2]
+  st1\\t{%1.<Vetype>}[%2], %0"
+  [(set_attr "simd_type" "simd_movgp, simd_dup, simd_store1s")
+   (set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")
+   (set_attr "simd_mode" "<MODE>")]
+)