iris/gfx12: Invalidate ISP at the end of every batch.

As requested by Ken since we're now (after 20e2c7308f674122)
re-emitting constants at the beginning of every batch which may lead
to some redundant constant restore overhead.  No statistically
significant performance changes observed with either change.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9903>

diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index e39fb7a..b60b05e 100644 (file)
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -541,6 +541,20 @@ finish_seqno(struct iris_batch *batch)
 static void
 iris_finish_batch(struct iris_batch *batch)
 {
+   const struct gen_device_info *devinfo = &batch->screen->devinfo;
+
+   if (devinfo->ver == 12 && batch->name == IRIS_BATCH_RENDER) {
+      /* We re-emit constants at the beginning of every batch as a hardware
+       * bug workaround, so invalidate indirect state pointers in order to
+       * save ourselves the overhead of restoring constants redundantly when
+       * the next render batch is executed.
+       */
+      iris_emit_pipe_control_flush(batch, "ISP invalidate at batch end",
+                                   PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE |
+                                   PIPE_CONTROL_STALL_AT_SCOREBOARD |
+                                   PIPE_CONTROL_CS_STALL);
+   }
+
    add_aux_map_bos_to_batch(batch);
 
    finish_seqno(batch);

diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h
index 5ac439a..a9f5cc6 100644 (file)
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -41,11 +41,12 @@ struct iris_context;
 /* The kernel assumes batchbuffers are smaller than 256kB. */
 #define MAX_BATCH_SIZE (256 * 1024)
 
-/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
- * or 12 bytes for MI_BATCH_BUFFER_START (when chaining).  Plus another
- * 24 bytes for the seqno write (using PIPE_CONTROL).
+/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END or 12
+ * bytes for MI_BATCH_BUFFER_START (when chaining).  Plus another 24 bytes for
+ * the seqno write (using PIPE_CONTROL), and another 24 bytes for the ISP
+ * invalidation pipe control.
  */
-#define BATCH_RESERVED 36
+#define BATCH_RESERVED 60
 
 /* Our target batch size - flush approximately at this point. */
 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)