#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
+#define DEFAULT_DMA_PBL 8
enum rx_frame_status { /* IPC status */
good_frame = 0,
priv->dev->dev_addr);
}
+static int stmmac_init_dma_engine(struct stmmac_priv *priv)
+{
+ int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
+
+ /* Some DMA parameters can be passed from the platform;
+ * in case of these are not passed we keep a default
+ * (good for all the chips) and init the DMA! */
+ if (priv->plat->dma_cfg) {
+ pbl = priv->plat->dma_cfg->pbl;
+ fixed_burst = priv->plat->dma_cfg->fixed_burst;
+ burst_len = priv->plat->dma_cfg->burst_len;
+ }
+
+ return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst,
+ burst_len, priv->dma_tx_phy,
+ priv->dma_rx_phy);
+}
+
/**
* stmmac_open - open entry point of the driver
* @dev : pointer to the device structure.
init_dma_desc_rings(dev);
/* DMA initialization and SW reset */
- ret = priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg->pbl,
- priv->plat->dma_cfg->fixed_burst,
- priv->plat->dma_cfg->burst_len,
- priv->dma_tx_phy, priv->dma_rx_phy);
+ ret = stmmac_init_dma_engine(priv);
if (ret < 0) {
pr_err("%s: DMA initialization failed\n", __func__);
goto open_error;
struct plat_stmmacenet_data plat_dat;
struct stmmac_mdio_bus_data mdio_data;
+struct stmmac_dma_cfg dma_cfg;
static void stmmac_default_data(void)
{
plat_dat.bus_id = 1;
plat_dat.phy_addr = 0;
plat_dat.interface = PHY_INTERFACE_MODE_GMII;
- plat_dat.dma_cfg->pbl = 32;
- plat_dat.dma_cfg->burst_len = DMA_AXI_BLEN_256;
plat_dat.clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat_dat.has_gmac = 1;
plat_dat.force_sf_dma_mode = 1;
mdio_data.phy_reset = NULL;
mdio_data.phy_mask = 0;
plat_dat.mdio_bus_data = &mdio_data;
+
+ dma_cfg.pbl = 32;
+ dma_cfg.burst_len = DMA_AXI_BLEN_256;
+ plat_dat.dma_cfg = &dma_cfg;
}
/**