MIPS: Rename BranchF functions.

BUG=

Review URL: https://codereview.chromium.org/1052653003

Cr-Commit-Position: refs/heads/master@{#27575}

diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index b23734a191d82f5a0fa2b90f04c89cc3162187c7..4247a84c5404fb6b47d2884a1c71a35e171f82ff 100644 (file)
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -858,8 +858,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
       UNSUPPORTED_COND(kMips64CmpS, branch->condition);
     }
     Label* nan = acceptNaN ? tlabel : flabel;
-    __ BranchFS(tlabel, nan, cc, i.InputSingleRegister(0),
-                i.InputSingleRegister(1));
+    __ BranchF32(tlabel, nan, cc, i.InputSingleRegister(0),
+                 i.InputSingleRegister(1));
 
     if (!branch->fallthru) __ Branch(flabel);  // no fallthru to flabel.
 
@@ -871,8 +871,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
       UNSUPPORTED_COND(kMips64CmpD, branch->condition);
     }
     Label* nan = acceptNaN ? tlabel : flabel;
-    __ BranchF(tlabel, nan, cc, i.InputDoubleRegister(0),
-               i.InputDoubleRegister(1));
+    __ BranchF64(tlabel, nan, cc, i.InputDoubleRegister(0),
+                 i.InputDoubleRegister(1));
 
     if (!branch->fallthru) __ Branch(flabel);  // no fallthru to flabel.
 

diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 3edf6e36bebf5ef1c8ff751b2eb1e9eb053b75c2..9297a533f3682891b1befe1de8dee8c589e2afd6 100644 (file)
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -923,8 +923,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
       UNSUPPORTED_COND(kMips64CmpS, branch->condition);
     }
     Label* nan = acceptNaN ? tlabel : flabel;
-    __ BranchFS(tlabel, nan, cc, i.InputSingleRegister(0),
-                i.InputSingleRegister(1));
+    __ BranchF32(tlabel, nan, cc, i.InputSingleRegister(0),
+                 i.InputSingleRegister(1));
 
     if (!branch->fallthru) __ Branch(flabel);  // no fallthru to flabel.
 
@@ -936,8 +936,8 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
       UNSUPPORTED_COND(kMips64CmpD, branch->condition);
     }
     Label* nan = acceptNaN ? tlabel : flabel;
-    __ BranchF(tlabel, nan, cc, i.InputDoubleRegister(0),
-               i.InputDoubleRegister(1));
+    __ BranchF64(tlabel, nan, cc, i.InputDoubleRegister(0),
+                 i.InputDoubleRegister(1));
 
     if (!branch->fallthru) __ Branch(flabel);  // no fallthru to flabel.
   } else {

diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index 2b6a25011b143c5566eaab61c99bbbf317216fee..24c698727603ac8382f81db9d4e87a8b2783ccbd 100644 (file)
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -1430,9 +1430,9 @@ void MacroAssembler::Mfhc1(Register rt, FPURegister fs) {
 }
 
 
-void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
-                                 Label* nan, Condition cc, FPURegister cmp1,
-                                 FPURegister cmp2, BranchDelaySlot bd) {
+void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target,
+                                   Label* nan, Condition cc, FPURegister cmp1,
+                                   FPURegister cmp2, BranchDelaySlot bd) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   if (cc == al) {
     Branch(bd, target);
@@ -1551,20 +1551,6 @@ void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
 }
 
 
-void MacroAssembler::BranchF(Label* target, Label* nan, Condition cc,
-                             FPURegister cmp1, FPURegister cmp2,
-                             BranchDelaySlot bd) {
-  BranchFSize(D, target, nan, cc, cmp1, cmp2, bd);
-}
-
-
-void MacroAssembler::BranchFS(Label* target, Label* nan, Condition cc,
-                              FPURegister cmp1, FPURegister cmp2,
-                              BranchDelaySlot bd) {
-  BranchFSize(S, target, nan, cc, cmp1, cmp2, bd);
-}
-
-
 void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) {
   if (IsFp64Mode()) {
     DCHECK(!src_low.is(at));

diff --git a/src/mips/macro-assembler-mips.h b/src/mips/macro-assembler-mips.h
index 37d8d308bb1bbfc377187926d333e7483c66177b..ac0a50b4e76e3016274613cc07893c492ce5058e 100644 (file)
--- a/src/mips/macro-assembler-mips.h
+++ b/src/mips/macro-assembler-mips.h
@@ -772,33 +772,38 @@ class MacroAssembler: public Assembler {
   void Mfhc1(Register rt, FPURegister fs);
 
   // Wrapper functions for the different cmp/branch types.
-  void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
-                   Condition cc, FPURegister cmp1, FPURegister cmp2,
-                   BranchDelaySlot bd = PROTECT);
-
-  void BranchF(Label* target,
-               Label* nan,
-               Condition cc,
-               FPURegister cmp1,
-               FPURegister cmp2,
-               BranchDelaySlot bd = PROTECT);
+  inline void BranchF32(Label* target, Label* nan, Condition cc,
+                        FPURegister cmp1, FPURegister cmp2,
+                        BranchDelaySlot bd = PROTECT) {
+    BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
+  }
 
-  void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
-                FPURegister cmp2, BranchDelaySlot bd = PROTECT);
+  inline void BranchF64(Label* target, Label* nan, Condition cc,
+                        FPURegister cmp1, FPURegister cmp2,
+                        BranchDelaySlot bd = PROTECT) {
+    BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd);
+  }
 
   // Alternate (inline) version for better readability with USE_DELAY_SLOT.
-  inline void BranchF(BranchDelaySlot bd,
-                      Label* target,
-                      Label* nan,
-                      Condition cc,
-                      FPURegister cmp1,
-                      FPURegister cmp2) {
-    BranchF(target, nan, cc, cmp1, cmp2, bd);
+  inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan,
+                        Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF64(target, nan, cc, cmp1, cmp2, bd);
   }
 
-  inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
-                       Condition cc, FPURegister cmp1, FPURegister cmp2) {
-    BranchFS(target, nan, cc, cmp1, cmp2, bd);
+  inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan,
+                        Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF32(target, nan, cc, cmp1, cmp2, bd);
+  }
+
+  // Alias functions for backward compatibility.
+  inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1,
+                      FPURegister cmp2, BranchDelaySlot bd = PROTECT) {
+    BranchF64(target, nan, cc, cmp1, cmp2, bd);
+  }
+
+  inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan,
+                      Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF64(bd, target, nan, cc, cmp1, cmp2);
   }
 
   // Truncates a double using a specific rounding mode, and writes the value
@@ -1632,6 +1637,11 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
   void Jr(Label* L, BranchDelaySlot bdslot);
   void Jalr(Label* L, BranchDelaySlot bdslot);
 
+  // Common implementation of BranchF functions for the different formats.
+  void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan,
+                     Condition cc, FPURegister cmp1, FPURegister cmp2,
+                     BranchDelaySlot bd = PROTECT);
+
   // Helper functions for generating invokes.
   void InvokePrologue(const ParameterCount& expected,
                       const ParameterCount& actual,

diff --git a/src/mips64/macro-assembler-mips64.cc b/src/mips64/macro-assembler-mips64.cc
index b6375c9e184a37ec2ac6921ddcff696bdbbd3581..759e990890b18de207aa455751dced6cb15bbf69 100644 (file)
--- a/src/mips64/macro-assembler-mips64.cc
+++ b/src/mips64/macro-assembler-mips64.cc
@@ -1629,9 +1629,9 @@ void MacroAssembler::Madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
 }
 
 
-void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
-                                 Label* nan, Condition cc, FPURegister cmp1,
-                                 FPURegister cmp2, BranchDelaySlot bd) {
+void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target,
+                                   Label* nan, Condition cc, FPURegister cmp1,
+                                   FPURegister cmp2, BranchDelaySlot bd) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   if (cc == al) {
     Branch(bd, target);
@@ -1749,20 +1749,6 @@ void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
 }
 
 
-void MacroAssembler::BranchF(Label* target, Label* nan, Condition cc,
-                             FPURegister cmp1, FPURegister cmp2,
-                             BranchDelaySlot bd) {
-  BranchFSize(D, target, nan, cc, cmp1, cmp2, bd);
-}
-
-
-void MacroAssembler::BranchFS(Label* target, Label* nan, Condition cc,
-                              FPURegister cmp1, FPURegister cmp2,
-                              BranchDelaySlot bd) {
-  BranchFSize(S, target, nan, cc, cmp1, cmp2, bd);
-}
-
-
 void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) {
   DCHECK(!src_low.is(at));
   mfhc1(at, dst);

diff --git a/src/mips64/macro-assembler-mips64.h b/src/mips64/macro-assembler-mips64.h
index 887b81dc57062a5f091b18cf6e3e354c5cc4dc57..e169e0c23b5bdd9769312efa06481000ab738b5d 100644 (file)
--- a/src/mips64/macro-assembler-mips64.h
+++ b/src/mips64/macro-assembler-mips64.h
@@ -802,33 +802,38 @@ class MacroAssembler: public Assembler {
               FPURegister scratch);
 
   // Wrapper functions for the different cmp/branch types.
-  void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
-                   Condition cc, FPURegister cmp1, FPURegister cmp2,
-                   BranchDelaySlot bd = PROTECT);
-
-  void BranchF(Label* target,
-               Label* nan,
-               Condition cc,
-               FPURegister cmp1,
-               FPURegister cmp2,
-               BranchDelaySlot bd = PROTECT);
+  inline void BranchF32(Label* target, Label* nan, Condition cc,
+                        FPURegister cmp1, FPURegister cmp2,
+                        BranchDelaySlot bd = PROTECT) {
+    BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
+  }
 
-  void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
-                FPURegister cmp2, BranchDelaySlot bd = PROTECT);
+  inline void BranchF64(Label* target, Label* nan, Condition cc,
+                        FPURegister cmp1, FPURegister cmp2,
+                        BranchDelaySlot bd = PROTECT) {
+    BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd);
+  }
 
   // Alternate (inline) version for better readability with USE_DELAY_SLOT.
-  inline void BranchF(BranchDelaySlot bd,
-                      Label* target,
-                      Label* nan,
-                      Condition cc,
-                      FPURegister cmp1,
-                      FPURegister cmp2) {
-    BranchF(target, nan, cc, cmp1, cmp2, bd);
+  inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan,
+                        Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF64(target, nan, cc, cmp1, cmp2, bd);
   }
 
-  inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
-                       Condition cc, FPURegister cmp1, FPURegister cmp2) {
-    BranchFS(target, nan, cc, cmp1, cmp2, bd);
+  inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan,
+                        Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF32(target, nan, cc, cmp1, cmp2, bd);
+  }
+
+  // Alias functions for backward compatibility.
+  inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1,
+                      FPURegister cmp2, BranchDelaySlot bd = PROTECT) {
+    BranchF64(target, nan, cc, cmp1, cmp2, bd);
+  }
+
+  inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan,
+                      Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchF64(bd, target, nan, cc, cmp1, cmp2);
   }
 
   // Truncates a double using a specific rounding mode, and writes the value
@@ -1701,6 +1706,11 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
   void Jr(Label* L, BranchDelaySlot bdslot);
   void Jalr(Label* L, BranchDelaySlot bdslot);
 
+  // Common implementation of BranchF functions for the different formats.
+  void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan,
+                     Condition cc, FPURegister cmp1, FPURegister cmp2,
+                     BranchDelaySlot bd = PROTECT);
+
   // Helper functions for generating invokes.
   void InvokePrologue(const ParameterCount& expected,
                       const ParameterCount& actual,