arm64: dts: qcom: sdm845: Fill in GENI DMA references
authorBjorn Andersson <bjorn.andersson@linaro.org>
Sun, 17 Jul 2022 03:44:01 +0000 (20:44 -0700)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Tue, 19 Jul 2022 04:33:28 +0000 (23:33 -0500)
The I2C and SPI might be configured in GPI DMA mode, fill in the
properties needed for this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220717034403.2135027-2-bjorn.andersson@linaro.org
arch/arm64/boot/dts/qcom/sdm845.dtsi

index 5912ca7..f0e2867 100644 (file)
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config", "qup-memory";
+                               dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                        };
 
                        spi15: spi@a9c000 {
                                interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
                                                <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };