#define _BCNSPACE_MSK 0x0FFF
#define _BCNSPACE_SHT 0
-
#endif /* __RTL8712_CMDCTRL_BITDEF_H__*/
#ifndef __RTL8712_MACSETTING_BITDEF_H__
#define __RTL8712_MACSETTING_BITDEF_H__
-
/*MACID*/
/*BSSID*/
/*BUILDUSER*/
-
-
#endif /* __RTL8712_MACSETTING_BITDEF_H__*/
#define BUILDTIME (RTL8712_MACIDSETTING_ + 0x0024)
#define BUILDUSER (RTL8712_MACIDSETTING_ + 0x0028)
-
-
#endif /*__RTL8712_MACSETTING_REGDEF_H__*/
#define MCS_TXAGC7 (RTL8712_RATECTRL_ + 0x67)
#define CCK_TXAGC (RTL8712_RATECTRL_ + 0x68)
-
#endif /*__RTL8712_RATECTRL_REGDEF_H__*/
#define _RXUSEDK BIT(1)
#define _TXUSEDK BIT(0)
-
#endif /*__RTL8712_SECURITY_BITDEF_H__*/
#define RTL8712_IOBASE_FF 0x10300000 /*IOBASE_FIFO 0x1031000~0x103AFFFF*/
-
/*IOREG Offset for 8712*/
#define RTL8712_SYSCFG_ RTL8712_IOBASE_IOREG
#define RTL8712_CMDCTRL_ (RTL8712_IOBASE_IOREG + 0x40)
#define RTL8712_DEBUGCTRL_ (RTL8712_IOBASE_IOREG + 0x310)
#define RTL8712_OFFLOAD_ (RTL8712_IOBASE_IOREG + 0x2D0)
-
/*FIFO for 8712*/
#define RTL8712_DMA_BCNQ (RTL8712_IOBASE_FF + 0x10000)
#define RTL8712_DMA_MGTQ (RTL8712_IOBASE_FF + 0x20000)
#define RTL8712_DMA_H2CCMD (RTL8712_IOBASE_FF + 0x90000)
#define RTL8712_DMA_C2HCMD (RTL8712_IOBASE_FF + 0xA0000)
-
/*------------------------------*/
/*BIT 16 15*/
* Block's Bandgap.
*/
-
/*--------------------------------------------------------------------------*/
/* SPS1_CTRL bits (Offset 0x18-1E, 56bits)*/
/*--------------------------------------------------------------------------*/
#define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/
#define SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/
-
/*----------------------------------------------------------------------------*/
/* LDOA15_CTRL bits (Offset 0x20, 8bits)*/
/*----------------------------------------------------------------------------*/
#define LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/
-
/*----------------------------------------------------------------------------*/
/* 8192S LDOV12D_CTRL bit (Offset 0x21, 8bits)*/
/*----------------------------------------------------------------------------*/
/*CLK_PS_CTRL*/
#define _CLK_GATE_EN BIT(0)
-
/* EFUSE_CTRL*/
#define EF_FLAG BIT(31) /* Access Flag, Write:1;
* Read:0
#ifndef __RTL8712_SYSCFG_REGDEF_H__
#define __RTL8712_SYSCFG_REGDEF_H__
-
#define SYS_ISO_CTRL (RTL8712_SYSCFG_ + 0x0000)
#define SYS_FUNC_EN (RTL8712_SYSCFG_ + 0x0002)
#define PMC_FSM (RTL8712_SYSCFG_ + 0x0004)
#define RCLK_MON (RTL8712_SYSCFG_ + 0x003E)
#define EFUSE_CLK_CTRL (RTL8712_SYSCFG_ + 0x02F8)
-
#endif /*__RTL8712_SYSCFG_REGDEF_H__*/
/*BCNERRTH*/
/*MLT*/
-
#endif /* __RTL8712_TIMECTRL_BITDEF_H__*/
#define _RPT_CNT_MSK 0x000FFFFF
#define _RPT_CNT_SHT 0
-
#endif /*__RTL8712_WMAC_BITDEF_H__*/
RT_CHANNEL_DOMAIN_MAX,
};
-
struct SetChannelPlan_param {
enum _RT_CHANNEL_DOMAIN ChannelPlan;
};
u8 datarates[NumRates];
};
-
/*
* Caller Mode: Any
* AP: AP can use the info for the contents of beacon frame
#define OID_802_11_PMKID 0x0d010123
#endif
-
/* For DDK-defined OIDs*/
#define OID_NDIS_SEG1 0x00010100
#define OID_NDIS_SEG2 0x00010200
#endif /* _RTL871X_MP_IOCTL_C_ */
-
enum MP_MODE {
MP_START_MODE,
MP_STOP_MODE,
#ifndef __RTL871X_MP_PHY_REGDEF_H
#define __RTL871X_MP_PHY_REGDEF_H
-
/*--------------------------Define Parameters-------------------------------*/
/*============================================================
#define ANTENNA_C 0x4
#define ANTENNA_D 0x8
-
/* accept all physical address */
#define RCR_AAP BIT(0)
#define RCR_APM BIT(1) /* accept physical match */
/*--------------------------Define Parameters-------------------------------*/
-
#endif /*__INC_HAL8192SPHYREG_H */
#define NUM_STA 32
#define NUM_ACL 64
-
/* if mode ==0, then the sta is allowed once the addr is hit.
* if mode ==1, then the sta is rejected once the addr is non-hit.
*/
#define _CAPABILITY_ 2
#define _TIMESTAMP_ 8
-
/*-----------------------------------------------------------------------------
* Below is the definition for WMM
*------------------------------------------------------------------------------