Add test cases for large integer legalization of add and sub. NFC

llvm-svn: 331604

diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll
index 7bd0b9d..e07727e 100644 (file)
--- a/llvm/test/CodeGen/X86/addcarry.ll
+++ b/llvm/test/CodeGen/X86/addcarry.ll
@@ -1,6 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
+define i128 @add128(i128 %a, i128 %b) nounwind {
+; CHECK-LABEL: add128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %rdx, %rdi
+; CHECK-NEXT:    adcq %rcx, %rsi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    retq
+entry:
+  %0 = add i128 %a, %b
+  ret i128 %0
+}
+
+define i256 @add256(i256 %a, i256 %b) nounwind {
+; CHECK-LABEL: add256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addq %r9, %rsi
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT:    adcq {{[0-9]+}}(%rsp), %r8
+; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    movq %rsi, (%rdi)
+; CHECK-NEXT:    movq %rcx, 16(%rdi)
+; CHECK-NEXT:    movq %r8, 24(%rdi)
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = add i256 %a, %b
+  ret i256 %0
+}
+
 define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind {
 ; CHECK-LABEL: a:
 ; CHECK:       # %bb.0: # %entry

diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll
index 862d489..90d4caa 100644 (file)
--- a/llvm/test/CodeGen/X86/subcarry.ll
+++ b/llvm/test/CodeGen/X86/subcarry.ll
@@ -1,6 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
+define i128 @sub128(i128 %a, i128 %b) nounwind {
+; CHECK-LABEL: sub128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq %rdx, %rdi
+; CHECK-NEXT:    sbbq %rcx, %rsi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    retq
+entry:
+  %0 = sub i128 %a, %b
+  ret i128 %0
+}
+
+define i256 @sub256(i256 %a, i256 %b) nounwind {
+; CHECK-LABEL: sub256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq %r9, %rsi
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT:    sbbq {{[0-9]+}}(%rsp), %r8
+; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    movq %rsi, (%rdi)
+; CHECK-NEXT:    movq %rcx, 16(%rdi)
+; CHECK-NEXT:    movq %r8, 24(%rdi)
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = sub i256 %a, %b
+  ret i256 %0
+}
+
 %S = type { [4 x i64] }
 
 define %S @negate(%S* nocapture readonly %this) {